PCIe 2.0 controller IP
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26
IP
from 8 vendors
(1
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10)
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Compute Express Link (CXL) 2.0 Controller
- Supports the CXL 2.0 specification
- Implements the CXL.io, CXL.mem, and CXL.cache protocols
- Supports all 3 defined CXL device types
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Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- Supports the latest CXL specification
- AMBA AXI Layer for CXL.io
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CCIX 1.1 Controller
- Track record of silicon proven PCIe 4.0 designs guarantees first-time silicon success
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PCI Express (PCIe) 2.1 Controller
- Compliant with PCIe 2.1 and 1.1 specifications
- Configurable as Root Complex, Endpoint, or Dual Mode
- Ultra-low transmit/receive latency and high bandwidth
- Supports x1, x2, x4, x8, and x16 configurations
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CCIX 1.1 Controller with AMBA AXI interface
- Controller IP for PCIe 5.0, 4.0, 3.1/3.0 Supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations, with CCIX ESM Support and AMBA AXI Interconect User Interface
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CXL 2.0 Dual Mode Controller
- Compatible with CXL 2.0 specification and backward compatible with CXL V1.0 and CXL V1.1
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Compute Express Link (CXL) 1.1/2.0/3.0 Controller
- Implements CXL 3.0 Specification at 64 GT/s
- Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
- Designed for easy integration with PipeCORE™ PCIe® PHY IP
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Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports key required features of the CXL 3.0 specification and full backwards compatibility with CXL 2.0, 1.0 and 1.1
- Supports PCIe 6.0 mode with 64 GT/s and x16 link width
- CXL license includes PCIe 6.0 functionality and fallback mode
- Customers using CXL do not need an additional PCIe 6.0 license
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CXL 3.0 IP
- Supports CXL 2.0, 1.1, and 1.0 specifications and is compliant with the PCIe 6.0 and offers backward compatibility with PCIe 5.0, 4.0, 3.1, 2.0, and 1.1
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PCIe2.0 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive: