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ONFI v5.0 NAND Flash IP

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  • ONFI 5.0 NAND Flash Controller IP Compliant to JEDEC
    • The NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash Interface (ONFI) Specification, revision 5.0, release candidate 0.5, dated 1 March 2021.
    • It is backwards compatible, supporting the Single Data Rate (asynchronous) mode, the double data rate moves NV-DDR, NV-DDR2, and NVDDR3, to include the latest NV-LPDDR4 recently introduced in the latest revision.
    Block Diagram -- ONFI 5.0 NAND Flash Controller IP Compliant to JEDEC
  • ONFI IO v5.0, 2.4GT/s, TSMC 16FFC, 1.2V, N/S orientation, H&V cell
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v5.0, 2.4GT/s, TSMC 16FFC, 1.2V, N/S orientation, H&V cell
  • ONFI IO v5.0, 2.4GT/s, TSMC 12FFC, 1.2V, N/S orientation, H&V cell
    • Supports ONFI 6.0(4.8Gbps), ONFI 5.1(3.6Gbps), ONFI 5.0(2.4Gbps), ONFI 4.1(1.2Gbps), ONFI 4.0(800Mbps) & ONFI 3.2(533Mbps)
    • Power-sequence free
    • Provides multi-driving-strength selection
    • Provides CTT mode and LTT mode
    Block Diagram -- ONFI IO v5.0, 2.4GT/s, TSMC 12FFC, 1.2V, N/S orientation, H&V cell
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