ONFI 3.2 NAND Controller IP
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ONFI 3.2 NAND Flash Controller
- - Compliant to ONFI revision 3.2 standard
- - Supports NV-DDR2 mode of operation supporting up to 200MHz
- - Supports NV-DDR mode of operation supporting up to 100MHz
- - Supports legacy Asynchronous devices operating from 10MHz to 50MHz
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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Advanced Flash Controller Interface Core
- Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
- Separate Administrative and I/O queues for flexible datapath management
- Maximum of 1 register write per command submission/ completion
- Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement