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NAND Flash IP

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Compare 109 IP from 31 vendors (1 - 10)
  • NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
    • The NAND Flash Controller Verification IP (VIP) is a specialized tool for validating and simulating NAND Flash memory interfaces in System-on-Chip (SoC) designs. It ensures compliance with protocols, error correction, and optimal performance across varied conditions.
    • This versatile tool supports a wide range of applications, including automotive, consumer electronics, industrial automation, and aerospace. By guaranteeing reliable integration of NAND Flash memory, it enables seamless functionality in devices ranging from gaming consoles to mission-critical systems
    Block Diagram -- NAND Flash Controller - Ensures robust NAND Flash interface validation for reliable designs
  • Open Nand Flash Interface (ONFI) Synthesizable Transactor
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications
    • Supports source synchronous and asynchronous data interfaces
    • Supports all mandatory and optional commands
    • Supports 16 bit bus width operations
    Block Diagram -- Open Nand Flash Interface (ONFI) Synthesizable Transactor
  • NAND Flash Synthesizable Transactor
    • Supports 100% of NAND Flash protocol standard of HY27UH08AG(5/D)M
    • Supports all the NAND Flash commands as per the specs
    • Supports NAND interface of x8 width
    • Supports multiplexed address/data
    Block Diagram -- NAND Flash Synthesizable Transactor
  • SPI NAND Flash Memory Model
    • Fully compatible with SPI Nand Flash standards.
    • Follows Nand Flash specification as defined in Micron specifications.
    • Supports all commands as per specifications.
    • Supports Master and Slave Mode
    Block Diagram -- SPI NAND Flash Memory Model
  • Open Nand Flash Interface (ONFI)
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications.
    • Supports Source Synchronous and Asynchronous data interfaces.
    • Supports all mandatory and optional commands.
    • Supports 16 bit bus width operations.
    Block Diagram -- Open Nand Flash Interface (ONFI)
  • NAND Flash Memory Model
    • Supports NAND Flash memory devices from all leading vendors.
    • Supports 100% of NAND FLASH protocol standard of HY27UH08AG(5/D)M.
    • Supports all the NAND FLASH commands as per the specs.
    • Provides cost effective solutions for mass storage applications.
    Block Diagram -- NAND Flash Memory Model
  • External NAND flash protection, designed to secure stored assets with a local key from PUF
    • PUFenc is designed to protect external flash memory and its stored assets.
    • The IP provides asset encryption, such as a learning model for AI or firmware for the chip with a local key from the PUF.
    • It adds an additional layer of security by avoiding using the global key, which is a shared key among ICs after the chip leaves the manufacturing floor.
    Block Diagram -- External NAND flash protection, designed to secure stored assets with a local key from PUF
  • NAND Flash Memory Controller with DMA
    • ONFI 4.0 support
    • BCH EDAC with up to 60 bits correction capacity per 1024 bytes chunks of data
    • Randomization of memory data
    • Basic timeout based SEFI detection and reporting
    Block Diagram -- NAND Flash Memory Controller with DMA
  • ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
    • ONFI v5.0 compliant + Up to 2.4GByte/s.
    • All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
    • Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
    • Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between
    Block Diagram -- ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
  • NAND Flash Controller
    • The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips.
    • It is designed with scalability in mind and provides standard AXI interface for the ease of integration in SoC design.
    • The NFC has many configurable features to support the requirements for different NAND Flash applications.
    Block Diagram -- NAND Flash Controller
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