MIPI SoundWire IP

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Compare 9 IP from 5 vendors (1 - 9)
  • MIPI SOUNDWIRE SLAVE
    • Compliant with MIPI SoundWire Standard 1.1x
    • SoundWire Host can support up to 11 Slaves.
    • Up to 8 Data Lanes supported
    • Slave-to-Slave transport supported
    Block Diagram -- MIPI SOUNDWIRE SLAVE
  • MIPI Soundwire PHY
    • MIPI specification for SoundWire V1.2
    • TSMC 12nm FFC
  • MIPI SoundWire Slave IP
    • Compliant with MIPI SOUNDWIRE version 1.1x Specification.
    • Full MIPI SOUNDWIRE Slave functionality.
    • Supports slave-to-slave transport
    • Supports upto 8 data lanes.
  • MIPI SoundWire Master IP
    • Compliant with MIPI SOUNDWIRE version 1.1x Specification.
    • Full MIPI SOUNDWIRE Master functionality
    • Host can supports upto 11 slaves.
    • Supports upto 8 data lanes.
  • MIPI SOUNDWIRE MASTER
    • Compliant with MIPI SoundWire Standard 1.1x
    • SoundWire Host can support up to 11 Slaves.
    • Up to 8 Data Lanes supported
    • Slave-to-Slave transport supported
    Block Diagram -- MIPI SOUNDWIRE MASTER
  • MIPI SoundWire Slave Controller 1.1
    • Compliant with latest draft MIPI SoundWire specification version 1.0
    • Flexible configuration for optimal gate count and power
    Block Diagram -- MIPI SoundWire Slave Controller 1.1
  • MIPI SoundWire Master Controller 1.1
    • Compliant with latest draft MIPI SoundWire specification version 1.0
    • Configurable number of Data Ports
    • Multi-lane Support with flexible Port <-> Lane mapping
    Block Diagram -- MIPI SoundWire Master Controller 1.1
  • Controller for MIPI Soundwire
    • MIPI compliant peripheral controller with multi-lane capability
    • APB Peripheral interface for control port and manager configuration registers
    • APB Initiator interface for external user defined registers
    Block Diagram -- Controller for MIPI Soundwire
  • MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
    • Compliant with MIPI DSI-2 Standard v0.8.x, MIPI D-PHY Standard v1.x, MIPI D-PHY Standard V2.x and MIPI C-PHY V1.x
    • Up to 3 Gsps per trio using C-PHY. 17Gbps in 3 Trios
    • Up to 2.5 Gbps per data lane of D-PHY (V2.0). 10Gbps in 4 Lanes
    • Programmable 1, 2, 3 (C-PHY) or 4 (D-PHY) Data Lane Configuration
    Block Diagram -- MIPI DSI-2 Transmitter v1.1 Controller IP, Compatible with MIPI D-PHY & C-PHY
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Semiconductor IP