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MIPI LLI IP

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Compare 13 IP from 4 vendors (1 - 10)
  • MIPI LLI Controller - (Low Latency Interface)
    • Compliant with MIPI LLI Rev 1.0 and M-PHY Type 1 Rev 2.0
    • Interfaces to on-chip interconnect infrastructure, like AHB or AXI or OCP buses
    • Configurable to provide any or all of the following interfaces for the named traffic classes
    • Provides AHB/AXI/OCP Slave Interface for PHY Adapter Layer management
    Block Diagram -- MIPI LLI Controller - (Low Latency Interface)
  • MIPI M-PHY G4 Designed For TSMC 28nm HPC+
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 4.1
    • Supports M-PHY Type-I system
    • Support for Clock and Data Recovery Options
    Block Diagram -- MIPI M-PHY G4 Designed For TSMC 28nm HPC+
  • MIPI M-PHY - TSMC 40nm
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY - TSMC 40nm
  • MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
    • Supports MIPI® Alliance Specification for M- PHY® Version 4.1.
    • Dual-simplex point-to-point interface with ultra-low voltage differential signaling.
    • Slew-rate control for EMI reduction.
    Block Diagram -- MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
  • MIPI M-PHY Designed For GF 28nm
    • •Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY Designed For GF 28nm
  • MIPI M-PHY in SMIC 90LL
    • Supports MIPI Standard for M-PHY v3.0.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    Block Diagram -- MIPI M-PHY in SMIC 90LL
  • MIPI M-PHY in SMIC 130nm
    • Complies with MIPI Standard for M-PHY v3.0
    • Slew-rate control for EMI reduction
    • Supports HS modes GEAR 1-3
    Block Diagram -- MIPI M-PHY in SMIC 130nm
  • MIPI M-PHY (HS-G3) in GF 28LP
    • Complies with MIPI Standard for M-PHY v3.0
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    Block Diagram -- MIPI M-PHY (HS-G3) in GF 28LP
  • MIPI M-PHY Designed For TSMC 28nm
    • •Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY Designed For TSMC 28nm
  • MIPI M-PHY Designed For TSMC 28nm
    • •Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
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