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MIPI DigRF IP

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Search (13)
Compare 13 IP from 3 vendors (1 - 10)
  • MIPI DigRF Verification IP
    • Supports 1.2 MIPI DIGRF Specification.
    • Supports both Data and Control frames
    • Supports frames nesting
    • Supports up to four lanes
    Block Diagram -- MIPI DigRF Verification IP
  • MIPI M-PHY DigRF Compliant IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.00- r02 and DigRF v4 V1.10.00.0.04
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports HS mode (GEAR 1-2, A & B)
    Block Diagram -- MIPI M-PHY DigRF Compliant IP
  • MIPI M-PHY in TSMC 65LP
    • Supports the MIPI Standard for M-PHY, Draft Specification v0.90.00-r02 and DigRF v4 V1.10.00.0.04
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports HS mode (GEAR 1-2, A & B)
    Block Diagram -- MIPI M-PHY in TSMC 65LP
  • MIPI M-PHY in SMIC 130nm
    • Complies with MIPI Standard for M-PHY v3.0
    • Slew-rate control for EMI reduction
    • Supports HS modes GEAR 1-3
    Block Diagram -- MIPI M-PHY in SMIC 130nm
  • MIPI M-PHY (HS-G3) in GF 28LP
    • Complies with MIPI Standard for M-PHY v3.0
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    Block Diagram -- MIPI M-PHY (HS-G3) in GF 28LP
  • MIPI M-PHY Compliant (HS-G2) IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports all HS modes (GEAR 1-2)
    Block Diagram -- MIPI M-PHY Compliant (HS-G2) IP
  • MIPI MPHY v3.1, 1Tx-1Rx Type-1, SMIC 40LL, N/S orientation
    • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
    • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
    • Burst mode CDR with short sync length (< 16SI)
    • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
    Block Diagram -- MIPI MPHY v3.1, 1Tx-1Rx Type-1, SMIC 40LL, N/S orientation
  • MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
    • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
    • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
    • Burst mode CDR with short sync length (< 16SI)
    • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
    Block Diagram -- MIPI MPHY v3.1, 2Tx-2Rx Type-1, UMC 22ULL 1.8V, N/S orientation
  • MIPI MPHY v3.1, 1Tx-1Rx Type-1, TSMC 55LP,
    • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
    • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
    • Burst mode CDR with short sync length (< 16SI)
    • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
    Block Diagram -- MIPI MPHY v3.1, 1Tx-1Rx Type-1, TSMC 55LP,
  • MIPI MPHY v3.1, 2Tx-2Rx Type-1, TSMC 28HPC+, N/S orientation
    • Supports RMMI interface for applications such as UNIPRO protocol (UFS, CSI-3, DSI-2) and DigRF
    • High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B with scalable power consumptions
    • Burst mode CDR with short sync length (< 16SI)
    • Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
    Block Diagram -- MIPI MPHY v3.1, 2Tx-2Rx Type-1, TSMC 28HPC+, N/S orientation
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