IP Catalog > MIPI DSI V1.3 Controller

MIPI DSI V1.3 Controller IP

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  • DSI v1.3 Transmit IP Core
    • The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile application processor) using 1 to 4 D-PHYs depending on bandwidth needs.
    Block Diagram -- DSI v1.3 Transmit IP Core
  • DSI Receiver Controller
    • The DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobile display modules) with Type 1 to 4 architectures.
    • Serial connectivity to the mobile applications processor’s DSI host is implemented using 1 to 4 D-PHY’s (also available from Arasan), depending on display bandwidth needs.
    Block Diagram -- DSI Receiver Controller
  • DSI-2 TX/RX Controller
    • The DSI-2 TX/RX controller IP is optimized for low power, small size and high-speed interfaces between an application processor and display modules using either MIPI CPHY or MIPI DPHY.
    • The DSI-2 TX/RX Controller IP is fully compliant with the DSI v1.3 specification and supports the DPHY
    Block Diagram -- DSI-2 TX/RX Controller
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