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MIPI D-PHY RX+ IP

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Compare 210 IP from 21 vendors (1 - 10)
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
  • MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
  • MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in SMIC 55LL
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
  • MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
  • MIPI D-PHY Rx ONLY v1.1 @1.5ghz Ultra Low Power & Low Area for IoT & Wearables
    • Compliant with MIPI D-PHY Specification v2.5 with backwards compatibility for D-PHY v2.1, v1.2, and v1.1
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