MIPI CSE IP
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Simulation VIP for MIPI CSI-2
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Generates constrained-random bus traffic with predefined error injection at CSI-2, D-PHY, C-PHY and A-PHY levels
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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MIPI CSI-2 RX Controller
- Lane merging, virtual channel detection, and programmable data extraction
- Error detection and correction, including packet-level and protocol decoding errors
- Supports all pixel formats defined in the CSI-2 standard
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
- Support CSI2, DSI2, I2C, GPIO,eDP/DP, and SPI as Protocols later
- For Functional safety, CSE & DSE are supported
