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MIPI C-PHY IP

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Compare 131 IP from 15 vendors (1 - 10)
  • MIPI C-PHY V1.1 TSMC 28nm HPC+
    • Compliant to MIPI Alliance Standard for C-PHY specification Version 1.0
    • Supports standard PHY transceiver compliant to MIPI Specification
    Block Diagram -- MIPI C-PHY V1.1 TSMC 28nm HPC+
  • MIPI C-PHY v1.1
    • Compliant to MIPI Alliance Standard for C-PHY specification Version 1.0
    • Supports standard PHY transceiver compliant to MIPI Specification
    Block Diagram -- MIPI C-PHY v1.1
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
    • Low power consumption, small area
    • Supports both overdrive (0.85V) and normal (0.75V) power
    • Support for various lane configurations
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm
    • Samsung Foundry 4nm low power enhanced (LN04LPE) CMOS device technology
    • 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 4nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
    • Samsung Foundry 5nm low power enhanced (LN05LPE) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 5nm
  • MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
    • Supports MIPI Specification for C-PHY Version 1.1
    • 80 Msps to 2.5 Gsps data rate in high speed mode
    Block Diagram -- MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
  • MIPI C-PHY
    •  Samsung Foundry 5nm low power enhanced (LN05LPE) CMOS device technology
    •  1.2V±5%, 0.75/0.85V±5% power supply
    •  Fully supports MIPI C-PHY v2.1 HS/LP/ULPS TX/RX (Backward Compatible with previous versions)
    Block Diagram -- MIPI C-PHY
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 8nm
    • Samsung Foundry 5nm low power enhanced (8LPU) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.75/0.85V±5% power supply
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY 8nm
  • MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
    • Compliant with the latest MIPI C-PHY and D-PHY specifications
    • Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
    • D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
    • C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
  • MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N3E, N3P)
    • Compliant with the latest MIPI C-PHY and D-PHY specifications
    • Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
    • D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
    • C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes
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