Mddi IP

QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps.
It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.

SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MAC (Media Access Controller) to a PHY (Physical Layer Device).
It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.

The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements for operation of 10/100 Mbps Ethernet/IEEE 802.3-2008 compliant node, and provides interface between the AHB or AXI Interface and the Media Independent Interface (MII) for the Ethernet operation.
Optionally the core supports RMII (Reduced MII Interface) and SMII (Serial MII Interface) for reducing the pin count to interface with external PHY device.

Up to four ports of concurrent traffic with an aggregate bandwidth of 100G are supported by one core (1x100G, 2x50G, 2x40G, 4x25G, 4x10G, 4x1G, 1x50G+2x25G)
Line rate operation
Flexible control/non-control port filtering
Configurable number of Secure Channels (SCs) and Security Associations (SAs) per physical port

Programmable application-side FIFO sizes (or complete bypass ) on TX, RX or both for easy integration with application logic
Packing and unpacking logic for application to internal data path matching
Supports line rate with minimum IFG
Memory-based statistics counter implementation for Area/gate savings

Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
The controller provides half- or full-duplex operation, supports jumbo frames, and optionally provides a useful set of statistics counters enabling station management.
Furthermore, the core can optionally be configured with a hardware timestamping unit enabling support for the IEEE 1588 precision time protocol (PTP).

Conforms to IEEE 802.3-2002 specification
Configurable width CPU interface with little or big endianess:
Simple interface allows easy connection to CPU
Narrow address bus (4 bits) with indirect I/O interfaceÂ for transmitted and received data dual port memories

MDDI IP