CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and programmable to support “any rate on any channel” (800G/600G/400G/200G/100G/50G/25G/10G/1G). It uses a novel time-sliced architecture that affords maximum density for high port count applications while maintaining industry-leading latencies that are optimized for data center applications.
In addition to being compliant with the IEEE 802.3bs, IEEE 802.3-2012, 25G/50G Ethernet Consortium, IEEE 802.3by, and OIF Flex-E Standards, CoMira also offers non-standard and application-driven protocols and modes of operation that allow us to tailor each IP configuration to a customer’s specific needs. This, in turn, lets them better differentiate their own end products.
CoMira’s encoding and security IPs are available as seamless configuration add-on options that can be included with the UMAC IP.
Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC)
Overview
Key Features
- Programmable application-side FIFO sizes (or complete bypass ) on TX, RX or both for easy integration with application logic
- Packing and unpacking logic for application to internal data path matching
- Supports line rate with minimum IFG
- Memory-based statistics counter implementation for Area/gate savings
- IP core clock is independent of line rate and can be asynchronous to both the SerDes and application clocks
- Support for SerDes with parallel interfaces of multiple bit widths
- Virtual Lane Mapping (VLM) support of multiple SerDes
- Support for flow control using either standard or priority pause frames
- Jumbo frame support
- Per Frame IFG on transmit for frame pacing
- Per frame configurable preamble on transmit
- Per frame preamble extraction on receive
- Custom preamble length
- Frame time stamping on both transmit and receive
- Optional custom header insertion
- Per frame CRC control/CRC stomping
- Configurable statistics counters from 32 to 90+ per channel depending on application requirements
Block Diagram
Technical Specifications
Related IPs
- media access control (MAC) address filtering
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- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- 25G LL MAC /PCS Ethernet IP for FPGA
- 25Gbps Ethernet and CPRI-10 FEC Layer IP Core
- Media Access Control Security (MACSec)