IP Catalog > LIN Controller

LIN Controller IP

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Compare 12 IP from 8 vendors (1 - 10)
  • Host / Device LIN controller
    • Implements the LIN 2.0, 2.1 and 2.2A protocols
    • Backward Compatible to LIN 1.3
    • Fully Programmable to operate in Host or Device Mode
    • Simple interfaces to the system through AMBA-APB, AMBA-AHB or other SRAM like interfaces
    Block Diagram -- Host / Device LIN controller
  • LIN Controller IP
    • Compliant with 2.2A LIN Specification
    • Full LIN transmit and receive functionality
    • Supports configurable master or slave functionality
    • Supports all frame types
  • LIN 2.2, 2.1 and 1.3 Protocol Controller IP
    • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
    Block Diagram -- LIN 2.2, 2.1 and 1.3 Protocol Controller IP
  • LIN Bus Controller – Basic and Safety-Enhanced
    • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
  • Local Interconnect Network (LIN) Soft Controller IP
    • Conforms with LIN 1.3, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
  • Block Diagram -- LIN Master Slave Controller
  • LIN Bus Master/Slave Controller Core
    • Support of LIN specifications 2.0, 2.1, and 2.2A
    • Configurable for support of master or slave functionality
    • Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master)
    • Automatic bit-rate detection (for slave)
    Block Diagram -- LIN Bus Master/Slave Controller Core
  • LINFlexD Controller
    • Fractional baud rate generator
    • Three operating modes for power saving
    • Loopback mode for testing
    Block Diagram -- LINFlexD Controller
  • LPDDR3/4 Memory Controller IP
    • a. DDR3-LPDDR3 and DDR4-LPDDR4 modes up to 2133Mbps, and 2800Mbps,respectively
    • b. x16/x32 data path interface extendable
    • c. JEDEC 1.2V SSTL I/Os and 1.1V LVSTL I/Os
    • d. Multiple drive strengths adjustable
  • Scalable & Royalty-Free 32-bit CPU
    • Configurable 32-bit Harvard architecture
    • Performance up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz
    • Small footprint starting at 10.6k/6.8k ASIC gates
    Block Diagram -- Scalable & Royalty-Free 32-bit CPU
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