LIN Bus Master/Slave Controller

Overview

The LIN-CTRL core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured at run-time to operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus.

The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production-proven multiple times.

The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready.

Key Features

  • Support of LIN specifications 2.0, 2.1, and 2.2A
  • Backward compatible with LIN specification 1.3
  • Run-time configurable master or slave operation
  • Programmable data rate between 1 Kbit/s and 20 Kbit/s (for master)
  • Automatic bit-rate detection (for slave)
  • 8-byte data buffer
  • Optional clock and input synchronization for slave operation
  • Generic 8-bit microcontroller interface
  • Wrappers converting the generic microcontroller interface to AMBA APB or AHB are offered with the core
  • Fully synchronous design, available in Verilog, completely synthesizable
  • The LIN Controller synthesizes to approximate 4,400 to 5,900 gates depending on the technology
  • Robustly verified and multiple times production-proven IP core
  • Safety-Enhanced Version (optional)
  • Certified as ISO-26262 ASIL-D Ready
  • Implements ECC for SRAM and spatial redundancy – DMR or TMR for inner logic protection, including optional lockstep operation

Block Diagram

LIN Bus Master/Slave Controller Block Diagram

Technical Specifications

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Semiconductor IP