The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications. The LINFlexD manages a high number of LIN messages efficiently with a minimum of CPU load. The LINFlexD supports LIN protocol versions 1.3, 2.0, 2.1, and 2.2 and provides an 8-byte buffer for transmit/receive data. The LINFlexD provides a configurable, programmable DMA interface for transmit and receive data for both LIN and UART operating modes.
LINFlexD Controller
Overview
Key Features
- Fractional baud rate generator
- Three operating modes for power saving
- Loopback mode for testing
- LIN Mode:
- Supports LIN protocol versions 1.3, 2.0, 2.1, and 2.2
- Supports LIN master and slave modes
- Bit rates up to 20 Kbit/s
- Classic and enhanced checksum calculation and check
- Single 8-byte buffer or FIFO for transmission and reception
- Autonomous header handling and transmit/receive data handling in slave mode
- Supports up to 16 identifiers
- DMA interface with single channels for master mode transmit and receive and configurable numbers of channels for slave mode transmit and receive
- UART Mode:
- Full-duplex communication
- Programmable baud rate up to 25 Mbit/s
- Separate clock for baud rate calculation
- DMA interface with separate channels for transmit and receive
Block Diagram
Deliverables
- Verilog RTL source code
- Test bench with test suites
- Documentation including User's Guide and Integration Guide
- Technology-independent synthesis constraints
Technical Specifications
Maturity
Silicon Proven
Availability
now