Local Interconnect Network (LIN) Soft Controller IP

Overview

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, primarily designed to be used in automotive applications. Compared to the CAN, The LIN is slower, but thanks to its simplicity, it is much more cost effective. Our Core is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of the CAN is not required. The DLIN core provides an interface between a microprocessor / microcontroller and LIN bus. It can work as a master or slave LIN node, depending on a work mode determined by the microprocessor / microcontroller. This controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3., LIN 2.1, and the newest 2.2 specification.

Key Features

Conforms with LIN 1.3, LIN 2.1 and LIN 2.2 specification.
Automatic LIN Header handling
Automatic Re-synchronization
Data rate between 1Kbit/s and 20 Kbit/s
Master and Slave work mode
Time-out detection
Extended error detection
“Break-in-data” support
Available system interface wrappers:
AMBA – APB Bus
Altera Avalon Bus
Xilinx OPB Bus

Applications

Automotive
Industrial
Embedded communication systems

Deliverables

Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support

Technical Specifications

Foundry, Node

Independent, suitable to all 3rd party PHY's

Maturity

In Production

Availability

Immediate

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