IEEE 802.1AE IP
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10)
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IEEE 802.1ae MACSEC IP Core for 40 Gbit Ethernet
- Complies with IEEE 802.1ae standard
- Based on the Algotronix AES-GCM-40G product
- Supports 256 bit keys as standard
- Targets high performance FPGA families from Xilinx and Altera.
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IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
- Complies with IEEE 802.1ae standard
- Based on the Algotronix AES-GCM-1G product
- Supports 128 bit keys as standard, with 256 bit key option available
- Targets all modern FPGA families from Xilinx, Altera, Microsemi and Lattice
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Multiple SecY IEEE 802.1ae MACSEC IP Core for 40Gbit Ethernet
- Complies with IEEE 802.1ae standard
- Based on the Algotronix AES-GCM-1G product
- Supports 128 bit keys as standard, with 256 bit key option available
- Targets all modern FPGA families from Xilinx, Altera, Microsemi and Lattice
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IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
- Small size combined with high performance
- Self-contained
- Very low latency
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IEEE 802.1ae (MACsec) Security Processor
- Small size combined with high performance:
- Self-contained, uses two external memories for key storage and statistic counters
- Very low latency
- Back-to-back packet processing
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AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
- Small size: Starting at less than 13K ASIC gates, 1.5 Gbps performance at less than 20K gates
- Scalability to throughputs of 128 bits per clock with the capability of parallel cores at throughputs of 100 Gbps and above
- Supports Galois Counter Mode Encryption and authentication (GCM-AES a.k.a. AES-GCM)
- Includes AES-GCM encryption, AES-GCM decryption, key expansion and data interface
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P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
- Small size: From 70K ASIC gates (at throughput of 18.2 bits per clock)
- 500 MHz frequency in 90 nm process
- Easily parallelizable to achieve higher throughputs
- Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
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Combo P1619 / 802.1ae (MACSec) GCM-AES/LRW-AES Cores
- Small size: from 31,000 ASIC gates for GLM1 from 58,000 ASIC gates for GLM2
- 400 MHz frequency in 130 nm process GLM1 throughput is 12.8 bits per clock GLM2 throughput is 25.6 bits per clock
- Easily parallelizable to achieve higher throughputs
- Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
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10M End Station Controller
- The 10M End Station Controller IP is a comprehensive hardware and software solution. It contains a Media Access Controller (MAC), a Time Of Day (TOD) system and an optional MACsec protection block.
- The solution can interface with nearly any microcontroller or embedded processor system, either via SPI or AXI Memory Mapped host interface. The host interface can simultaneously transfer both transmit and receive packets, and the End Station Controller supports store and forward or cut-through packet handling.
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100G / 200G / 400G / 800G / 1.6T MACsec
- The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
- It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks.
- The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
