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High-Speed SerDes IP

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Compare 87 IP from 22 vendors (1 - 10)
  • 64G High-speed SerDes
    • The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane
    • The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings
    Block Diagram -- 64G High-speed SerDes
  • High-Speed LVDS (SERDES) Transceiver
    • The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
    • The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.
    Block Diagram -- High-Speed LVDS (SERDES) Transceiver
  • SerDes
    • High-speed SerDes with ultra-low-power consumption
    • Industry’s fastest die to die communications
    • Multiprotocol SerDes: HMC, PCIe, SATA, SAS, and USB and more
    • High lane count with multiple data rates supported
  • Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • Programmable Low Power SERDES Receiver on TSMC CLN65LP
    • Programmable SERDES analog receiver that supports 0.6 to 3.75 Gbps standard serial protocols
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.8 mW/Gbps including termination
    • Minimal latency – 4 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
    • Compact form factor – 0.104 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.8 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN28HPL
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.095 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.6 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
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