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Ethernet PCS IP

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Compare 274 IP from 31 vendors (1 - 10)
  • Ethernet PCS 10G/25G
    • User controlled AutoNegotiation (IEEE 802.3 Clause 37) with full programmability
    • Support for 10G Energy-Efficient Ethernet (EEE) compliant with the IEEE, 802.3az specification
    Block Diagram -- Ethernet PCS 10G/25G
  • Ethernet PCS 1G/2.5G
    • Richly Featured
    • Delivering Performance
    • Easy to use
    • Silicon Agnostic
    Block Diagram -- Ethernet PCS 1G/2.5G
  • Ethernet PCS 100G
    • Highly Configurable
    • Delivering Performance
    • Silicon Agnostic
    Block Diagram -- Ethernet PCS 100G
  • 1.6T Ethernet PCS IP
    • Supports all required features of the IEEE 802.3 specification and draft specifications
    • IP available in single 1.6T mode and quad channel mode supporting 4 x 400G, 2 x 800G and 1.6T
    • Designed to be used with Synopsys 1.6T MAC IP for 1.6T Ethernet Systems
    • Includes RS-FEC functions
    Block Diagram -- 1.6T Ethernet PCS IP
  • 2.5Gbps Ethernet PCS IP Core
    • Implements the transmit, receive, and auto-negotiation functions of the IEEE 802.3z specification
    • 16-bit GMII interface operating at 156.25 MHz (2.5 Gbps)
    Block Diagram -- 2.5Gbps Ethernet PCS IP Core
  • 1Gb Ethernet PCS
    • Complete 1Gb Ethernet Physical Coding Sublayer Solution Based on the ORCA® ORT42G5 Device
    • IP Targeted to the ORT42G5 Programmable Array Section Implements Functionality Conforming to IEEE 803.2-2002
    • Ethernet Functionality Supported by the Embedded Section of the ORT42G5, including:
    • Simulation Models and Test Benches
    Block Diagram -- 1Gb Ethernet PCS
  • 10Gb Ethernet PCS
    • Complete 10Gb Ethernet Physical Coding Sublayer (PCS) Solution Based on the ORCA 10 Gbits/s Line Interface (ORLI10G) FPSC, Enabling Flexible10GbE LAN/WAN Application Solutions.
    • IP Targeted to the ORLI10G Programmable Array Section Implements Functionality Conforming to IEEE Standard 802.3ae, Including:
    • ORCA Bitstream Format Allows Direct Downloading and Turnkey Functionality.
    • ModelSim Simulation Models and Test Benches Available for Free Evaluation.
    Block Diagram -- 10Gb Ethernet PCS
  • 25G LL MAC /PCS Ethernet IP for FPGA
    • Ultra Low Latency 128 ns packet Round Trip Time (RTT) in Virtex® UltraScale™
    • Integrated FCS CRC32 check/generate
    Block Diagram -- 25G LL MAC /PCS Ethernet IP for FPGA
  • 25Gbit/s Ethernet PCS
    • Designed to IEEE 802.3by
    • Low Latency PCS/PMA (RTT) 99 ns
    • 5250 LUTs
    Block Diagram -- 25Gbit/s Ethernet PCS
  • SGMII and Gb Ethernet PCS
    • Implements PCS functions of the Cisco SGMII Specification, Revision 1.7
    • Implements PCS functions for IEEE 802.3z (1000BaseX)
    • Dynamically selects SGMII/1000BaseX PCS operation
    • Supports MAC or PHY mode for SGMII auto-negotiation
    Block Diagram -- SGMII and Gb Ethernet PCS
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