Ethernet PCS 100G

Overview

TheEthernet PCS 100G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification.

The Ethernet PCS 100G IP supports 100G line rates, however other Ethernet PCS speeds are available, such as 1G/2.5G and 10G/25G.

The Ethernet PCS 100G IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 4-lane parallel interface and offers a CGMII interface on the other side.

The Ethernet PCS 100G IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.

Key Features

Delivers Performance
- Supports Ethernet speed of 100G
- Complete 100GBASE-R with RS-FEC solution
- Can be used in common 100G Ethernet PHY applications
Feature Rich
- Configurable for several operating modes and speeds
- Works with multiple SerDes widths
- Clause 81 Reconciliation Sublayer (RS) and Media Independent Interface for 100 Gb/s operation (and CGMII)
- Clause 82 Physical Coding Sublayer (PCS) for 64B 66B, type 100GBASE-R
- Clause 91 Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
- Clause 45 Management Data Input/Output (MDIO) Interface
- 64B 66B encoding/decoding
- Time Synchronization can optionally be included
Highly Configurable
- BUS2IP is the default Slave PHY Management interface, with AXI, APB, MDIO being optional
- Easy interfacing to standard MACs
- Several common control bus standards are supported
- Can be delivered with integrated MAC for plug and play
- Includes test pattern Generator/Checker
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs

Block Diagram

Deliverables

The IP Core can be delivered in Source code or Encrypted format.
The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case and Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional).
- Synopsys Lint, CDC and Waivers (optional).

Technical Specifications

Maturity

Mature

Availability

Available

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