200G and 400G Ethernet PCS IP
Overview
The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of features that enable users to define an optimized PCS in products across a range of 400G/200G Ethernet applications. The Synopsys PCS IP is designed to work with Synopsys Ethernet MAC IP to deliver solutions for 200G & 400G Ethernet applications. The multi-channel, multirate PCS allows flexible use of the various lanes for different PMA interfaces. The IP also includes multiplexed Reed-Solomon Forward Error Correction (RS-FEC) functions for use by different channels at various speeds
Key Features
- Single port 400G/200G
- Quad 200G
- Octal 400G
Benefits
- Complaint with the IEEE 802.3bs standard
- 400G PCS available in single, quad or octal port supporting multiple 100G/50G/25G/10G SerDes lanes
- 200G PCS available in single or quad port supporting multiple 100G/50G/25G/10G SerDes lanes
- Designed to be used with Synopsys 400G and 200G Ethernet MAC IP for 400G/200G Ethernet systems
- Supports RS-FEC function
- Silicon proven
- Integration tested with the DesignWare 400G/200G Ethernet MAC and 112G Ethernet PHY IP
Applications
- High-Performance Networking
- High-Performance Computing
Deliverables
- SystemVerilog RTL Source code
- Verilog Testbench environment with example testcases
- Scripts and constraints files for implementation tools like Spyglass Lint/CDC, DesignCompiler, etc.
- IPXACT views for register maps
- Documentation: Databook, Integration User guide and Release Notes
Technical Specifications
Maturity
Available on request
Availability
Available