800G Ethernet PCS IP
Overview
The Synopsys 800G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the 400G IEEE 802.3bs standard, provides a complete set of features enabling users to define an optimized PCS in products across a range of 800G Ethernet applications. The PCS IP implements two standard 400G PCS (IEEE P802.3bs) with bonding to create an aggregate 800G PCS. The Synopsys 800G Ethernet PCS IP is available in single or octal port configurations. The IP in either configuration seamlessly interoperates with the Synopsys 112G Ethernet PHY IP. The IP includes multiplexed Reed-Solomon Forward Error Correction (RS-FEC) functions for use by different channels at various speeds. The IP implements a 1024-bit wide CDMII for connections to the Synopsys MAC on the application side and 8-lane interface to the Synopsys PHY on the Ethernet line side. Synopsys delivers a complete Ethernet solution with 800G Ethernet PCS IP, 800G Ethernet MAC IP and 112G Ethernet PHY IP.
Key Features
- Common and single port features
- Octal core features
Benefits
- Compliant with the IEEE 802.3 standard
- Configurable IP available in single or octal port
- Designed to be used with Synopsys 800G MAC IP for 800G Ethernet Systems
- Includes RS-FEC functions
- Supports IEEE 1588 standard
- Silicon proven
- Integration tested with the Synopsys 800G Ethernet MAC and 112G Ethernet PHY IP
Applications
- High-Performance Networking
- High-Performance Computing
Deliverables
- ystemVerilog RTL Source code
- Verilog Testbench environment with example testcases
- Scripts and constraints files for implementation tools like Spyglass Lint/CDC, DesignCompiler, etc.
- IPXACT views for register maps
Technical Specifications
Maturity
Available on request
Availability
Available