Ethernet controller IP

XEC is a high performance 1000M/100M/10M Ethernet Controller IP. It support GMII/RGMII/MII/RMII MAC-PHY interface and support AXI/AHB system bus.
XEC can receive the data from Ethernet PHY to the AXI/AHB bus, and to send out data from AXI/AHB bus to the Ethernet PHY.

The Ethernet Controller is an ASIC proven high-performance, feature-rich network interface solution designed to deliver reliable, low-latency Ethernet connectivity across a broad range of embedded and enterprise applications.
Comcores offers controllers ranging from 10M to 800G enabling seamless integration into systems requiring Ethernet connectivity.

XtremeSilica’s Ethernet Controllers support 1G to 800G speeds, ensuring accurate simulation and validation of Ethernet protocols for high-speed networks. With IEEE compliance, advanced features like QoS, VLAN, and error injection, they optimize performance for Ethernet-based SoC designs.
These controllers excel in diverse applications, including data centers, telecommunications, cloud computing, HPC, automotive Ethernet, and industrial automation. They provide seamless integration, high throughput, low latency, and robust networking for modern systems across industries.

High-performance DMA with advanced AXI offloading capabilities and descriptor caching, QoS, and IEEE1588
Time-Sensitive Networking/Audio-Video Bridging (TSN/AVB) functionality enables unified Ethernet communication of critical data without traffic congestion in shared networks
IEEE 802.3az Energy-Efficient Ethernet (EEE), VLAN, TCP/IP offload, and remote network monitoring (RMON)
Multiple client interfaces: AXI, AHB, with optional DMA support

Compliant with IEEE 802.3 and Ethernet Technology Consortium specifications
Integrated FEC support including RS (528,514), RS(544,514), Firecode, Ethernet Technology Consortium Low Latency RS FEC
Supports 802.3 PAUSE and 802.10bb Priority Flow Control (PFC) frame-based flow control, 802.3br Interspersing Express Traffic (IET) and IEEE 802.1AS Precision Time Protocol (PTP)
APB interface for management and control

To achieve gigabit transfer rates in real life and to make it possible to also use less powerful CPUs, AFEC has several features that help minimize the CPU load:
Other standard features of AFEC include:
The FPGA resource usage of AFEC is about 4,500 FPGA registers.

Compliant with IEEE 802.3 and Ethernet Technology Consortium specifications
Integrated FEC support including RS (528,514), RS(544,514), Firecode, Ethernet Technology Consortium Low Latency RS FEC
Supports 802.3 PAUSE and 802.10bb Priority Flow Control (PFC) frame-based flow control, 802.3br Interspersing Express Traffic (IET) and IEEE 802.1AS Precision Time Protocol (PTP)
APB interface for management and control

Compliant with IEEE 802.3 and Ethernet Technology Consortium specifications
Integrated FEC support including RS (528,514), RS(544,514), Firecode, Ethernet Technology Consortium Low Latency RS FEC
Supports 802.3 PAUSE and 802.10bb Priority Flow Control (PFC) frame-based flow control, 802.3br Interspersing Express Traffic (IET) and IEEE 802.1AS Precision Time Protocol (PTP)
APB interface for management and control

IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
Supports full- and half-duplex operation (selectable via a core configuration registers)
CSMA/CD protocol for half-duplex operation

Ethernet Controller IP