DisplayPort v1.4 IP
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10)
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
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Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
- DisplayPort version 1.4 compliant receiver
- PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate
- Integrated 100-ohm termination resistors with common-mode biasing
- Integrated equalizer with tunable strength
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eDP 1.5a RX PHY Samsung 14nm
- Compliant to DisplayPort v1.4, eDP v1.4, and eDP v1.5a
- Supports data rates from Reduced Bit Rate (RBR:1.62 Gbps) to High Bit Rate 3 (HBR3: 8.1Gbps), and user configurable custom B/Ws
- Supports for eDP v1.4b features, such as PSR1 and PSR2
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DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 28HPC+, N/S orientation
- Supports 1.62G to 20Gbps data rates and compact die area
- Supports x1, x2 and x4 lanes
- Supports post-cursor 1 FFE for Main Link transmitter
- Supports four swing levels for Main Link transmitter
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DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC 12FFC, N/S orientation
- Supports 1.62G to 20Gbps data rates and compact die area
- Supports x1, x2 and x4 lanes
- Supports post-cursor 1 FFE for Main Link transmitter
- Supports four swing levels for Main Link transmitter
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DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC N7, 1.8V, N/S orientation
- Supports 1.62G to 20Gbps data rates and compact die area
- Supports x1, x2 and x4 lanes
- Supports post-cursor 1 FFE for Main Link transmitter
- Supports four swing levels for Main Link transmitter
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DisplayPort TX v1.4, 8.1Gbps x2-lane, TSMC N6, 1.8V, N/S orientation
- Supports 1.62G to 20Gbps data rates and compact die area
- Supports x1, x2 and x4 lanes
- Supports post-cursor 1 FFE for Main Link transmitter
- Supports four swing levels for Main Link transmitter
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10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
- Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, QSGMII,and SGMII
- Supports PCIe L1 sub-states
- Supports SRIS and internal SSC generation
- Multi-protocol support for simultaneous independent links
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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
- Support for PCIe 1.1, 2.1, and 3.0
- Supports x1 configuration
- Compliant to PIPE 4.2 specification with configurable PIPE frequency
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Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in UMC 55SP
- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
