 array:1 [
  "searches" => array:3 [
    0 => array:11 [
      "q" => "DO-254 HDLC & SDLC"
      "query_by" => "text_high_priority, text_low_priority"
      "query_by_weights" => "100, 1"
      "max_candidates" => 10000
      "per_page" => 10
      "page" => 1
      "facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
      "max_facet_values" => 1000
      "sort_by" => "_text_match:desc"
      "prioritize_exact_match" => false
      "text_match_type" => "max_weight"
    ]
    1 => array:11 [
      "q" => "DO-254 HDLC & SDLC"
      "query_by" => "text_high_priority, text_low_priority"
      "query_by_weights" => "100, 1"
      "max_candidates" => 10000
      "per_page" => 10
      "page" => 1
      "facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
      "max_facet_values" => 1000
      "sort_by" => "_text_match:desc"
      "prioritize_exact_match" => false
      "text_match_type" => "max_weight"
    ]
    2 => array:11 [
      "q" => "DO-254 HDLC & SDLC"
      "query_by" => "text_high_priority, text_low_priority"
      "query_by_weights" => "100, 1"
      "max_candidates" => 10000
      "per_page" => 10
      "page" => 1
      "facet_by" => "provider.object, asic.foundry, asic.foundry_node, asic.node_foundry, asic.node, productTypes"
      "max_facet_values" => 1000
      "sort_by" => "_text_match:desc"
      "prioritize_exact_match" => false
      "text_match_type" => "max_weight"
    ]
  ]
]

 array:1 [
  "results" => array:3 [
    0 => array:8 [
      "facet_counts" => array:6 [
        0 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "{"id":3,"name":"CAST","providerslug":"cast"}"
              "value" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            ]
          ]
          "field_name" => "provider.object"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
        1 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        2 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry_node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        3 => array:4 [
          "counts" => []
          "field_name" => "asic.node_foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        4 => array:4 [
          "counts" => []
          "field_name" => "asic.node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        5 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "sip"
              "value" => "sip"
            ]
          ]
          "field_name" => "productTypes"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
      ]
      "found" => 1
      "hits" => array:1 [
        0 => array:5 [
          "document" => array:48 [
            "asic.foundry" => []
            "asic.foundry_node" => []
            "asic.foundry_node_process" => []
            "asic.node" => []
            "asic.node_foundry" => []
            "blockdiagram" => "/upload/catalog/product/blockdiagram/5709/icon_hdlc-amp-sdlc-protocol-controller-67d6755f17221.png.webp"
            "category.id" => array:1 [
              0 => 257
            ]
            "category.name" => array:1 [
              0 => "HDLC IP"
            ]
            "category.slug" => []
            "created_at" => 1399228486
            "id" => "5709"
            "keyfeatures" => """
              <ul>\r\n
              \t<li>Controller for both the SDLC and HDLC (ISO 13239) transmission protocols\r\n
              \t<ul>\r\n
              \t\t<li>Based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC), operating in SDLC Mode</li>\r\n
              \t\t<li>Additional features support HDLC and proprietary serial protocols.</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Safety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t<ul>\r\n
              \t\t<li>Implements TMR for all internal registers &nbsp;</li>\r\n
              \t\t<li>Delivered with a complete DO-254 Certification Data Package</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Frame Formatting\r\n
              \t<ul>\r\n
              \t\t<li>Programmable preamble pattern and preamble length</li>\r\n
              \t\t<li>Programmable inter-frame space</li>\r\n
              \t\t<li>Single- or double-byte address field</li>\r\n
              \t\t<li>Address filtering allowing multicast and broadcast</li>\r\n
              \t\t<li>Raw transmit and receive testing modes</li>\r\n
              \t\t<li>Back-to-back transmit &amp; back-to-back receive</li>\r\n
              \t\t<li>NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding &amp; Decoding</li>\r\n
              \t\t<li>Bit Stuffing and Bit Stripping</li>\r\n
              \t\t<li>16-bit (CRC-16, CCITT or IBM) and 32-bit (CRC-32) frame check sequence</li>\r\n
              \t\t<li>CRC, Bit-stuffing/stripping, and abort and idle sequences detection can be independently enabled/disabled</li>\r\n
              \t\t<li>Receiver FIFO Packet counter</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Serial Link Interface\r\n
              \t<ul>\r\n
              \t\t<li>Full or Half Duplex</li>\r\n
              \t\t<li>Programmable Baud Rate</li>\r\n
              \t\t<li>Modem Controls (RTSn/CTSn)</li>\r\n
              \t\t<li>Collision detection</li>\r\n
              \t\t<li>Internal baud generator, or external transmit clock with strobe</li>\r\n
              \t\t<li>Automatic receive clock recovery, or external receive clock with strobe</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Easy to Integrate\r\n
              \t<ul>\r\n
              \t\t<li>Suitable for interrupt-based or polling-based operation</li>\r\n
              \t\t<li>Configurable size, transmit &amp; receive FIFOs</li>\r\n
              \t\t<li>80XC152-like control&nbsp;status registers</li>\r\n
              \t\t<li>APB or AXI4-Lite</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              </ul>
              """
            "keyfeatures_cn" => ""
            "keywords" => ""
            "logo" => "cast-66bb475b9ffc0.webp"
            "logo2" => "cast-66bb475b9ffc0.webp"
            "name" => "asic.node"
            "overview" => """
              <p>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</p>\r\n
              \r\n
              <p>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;</p>\r\n
              \r\n
              <p>The controller&rsquo;s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud&nbsp;rate is programmable and limited only by the link drivers and the core&rsquo;s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. &nbsp;</p>\r\n
              \r\n
              <p>The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.</p>\r\n
              \r\n
              <p>The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.&nbsp;</p>
              """
            "overview_cn" => ""
            "partnumber" => "HSDLC"
            "priority" => 1
            "priority_taxo" => 1
            "productTypes" => array:1 [
              0 => "sip"
            ]
            "provider.id" => 3
            "provider.name" => "CAST"
            "provider.object" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            "provider.priority" => 751
            "provider.slug" => "cast"
            "published_as_new_at" => 0
            "seofeatures" => """
              <ul>\r\n
              \t<li>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols.</li>\r\n
              \t<li>It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</li>\r\n
              \t<li>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors.</li>\r\n
              </ul>
              """
            "seofeatures_cn" => ""
            "shortdescription" => "HDLC & SDLC Protocol Controller"
            "shortdescription_cn" => ""
            "slug" => "hdlc-amp-sdlc-protocol-controller-ip"
            "sortable_id" => 5709
            "taxo0" => array:1 [
              0 => 1
            ]
            "taxo1" => array:1 [
              0 => 6
            ]
            "taxo2" => array:1 [
              0 => 257
            ]
            "taxo3" => []
            "taxo4" => []
            "taxo5" => []
            "taxo6" => []
            "taxo7" => []
            "taxo8" => []
            "text_high_priority" => "HSDLC HDLC & SDLC Protocol Controller CAST"
            "text_low_priority" => """
              The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and Synchronous (SDLC) protocols. It is based on Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode  adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;\r\n
              \r\n
              The operates as peripheral easy integrate with both modern legacy processors. status registers are accessible via an APB generic 80C51-like bus interface comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;\r\n
              \r\n
              The controller&rsquo;s great flexibility enables variety serial link setups. provides two independent interfaces one transmitting receiving data. Both provide control drivers full- half-duplex can be programmed use hardware flow (RTS/CTS) it also detect collisions. baud&nbsp;rate programmable limited only by core&rsquo;s clock frequency. derives receive from received data uses externally provided clock. &nbsp;\r\n
              \r\n
              The available versions: Normal Safety-Enhanced. Safety-Enhanced version triple-modular redundancy (TMR) full immunity single-bit upsets errors complies Design Assurance Level A (DAL-A) DO-254 standard.\r\n
              \r\n
              The designed reuse rigorously verified scan-ready. Although manage links contains no latches tri-states fully synchronous single domain. Verilog RTL targeted FPGA netlist. Deliverables everything required successful implementation including sample scripts extensive testbench documentation.&nbsp; \r\n
              \tController (ISO 13239) protocols\r\n
              \t\r\n
              \t\tBased operating Mode\r\n
              \t\tAdditional protocols.\r\n
              \t\r\n
              \t\r\n
              \tSafety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t\r\n
              \t\tImplements TMR all internal &nbsp;\r\n
              \t\tDelivered complete Certification Package\r\n
              \t\r\n
              \t\r\n
              \tFlexible Frame Formatting\r\n
              \t\r\n
              \t\tProgrammable preamble pattern length\r\n
              \t\tProgrammable inter-frame space\r\n
              \t\tSingle- double-byte address field\r\n
              \t\tAddress filtering allowing multicast broadcast\r\n
              \t\tRaw transmit testing modes\r\n
              \t\tBack-to-back &amp; back-to-back receive\r\n
              \t\tNRZ NRZI Bi-Phase-S Manchester Encoding Decoding\r\n
              \t\tBit Stuffing Bit Stripping\r\n
              \t\t16-bit (CRC-16 CCITT IBM) 32-bit (CRC-32) check sequence\r\n
              \t\tCRC Bit-stuffing/stripping abort idle sequences detection independently enabled/disabled\r\n
              \t\tReceiver FIFO Packet counter\r\n
              \t\r\n
              \t\r\n
              \tFlexible Interface\r\n
              \t\r\n
              \t\tFull Half Duplex\r\n
              \t\tProgrammable Baud Rate\r\n
              \t\tModem Controls (RTSn/CTSn)\r\n
              \t\tCollision detection\r\n
              \t\tInternal baud generator external strobe\r\n
              \t\tAutomatic recovery strobe\r\n
              \t\r\n
              \t\r\n
              \tEasy Integrate\r\n
              \t\r\n
              \t\tSuitable polling-based operation\r\n
              \t\tConfigurable size FIFOs\r\n
              \t\t80XC152-like control&nbsp;status registers\r\n
              \t\tAPB AXI4-Lite\r\n
              \t\r\n
              \t\r\n
              """
            "text_medium_priority" => ""
            "updated_at" => 1742398313
          ]
          "highlight" => array:2 [
            "text_high_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
            "text_low_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
          ]
          "highlights" => array:2 [
            0 => array:3 [
              "field" => "text_low_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
            1 => array:3 [
              "field" => "text_high_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
          ]
          "text_match" => 1763176949298495490
          "text_match_info" => array:7 [
            "best_field_score" => "2211897868288"
            "best_field_weight" => 15
            "fields_matched" => 2
            "num_tokens_dropped" => 0
            "score" => "1763176949298495490"
            "tokens_matched" => 3
            "typo_prefix_score" => 0
          ]
        ]
      ]
      "out_of" => 18250
      "page" => 1
      "request_params" => array:4 [
        "collection_name" => "product_semiiphub"
        "first_q" => "DO-254 HDLC & SDLC"
        "per_page" => 10
        "q" => "DO-254 HDLC & SDLC"
      ]
      "search_cutoff" => false
      "search_time_ms" => 1
    ]
    1 => array:8 [
      "facet_counts" => array:6 [
        0 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "{"id":3,"name":"CAST","providerslug":"cast"}"
              "value" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            ]
          ]
          "field_name" => "provider.object"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
        1 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        2 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry_node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        3 => array:4 [
          "counts" => []
          "field_name" => "asic.node_foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        4 => array:4 [
          "counts" => []
          "field_name" => "asic.node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        5 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "sip"
              "value" => "sip"
            ]
          ]
          "field_name" => "productTypes"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
      ]
      "found" => 1
      "hits" => array:1 [
        0 => array:5 [
          "document" => array:48 [
            "asic.foundry" => []
            "asic.foundry_node" => []
            "asic.foundry_node_process" => []
            "asic.node" => []
            "asic.node_foundry" => []
            "blockdiagram" => "/upload/catalog/product/blockdiagram/5709/icon_hdlc-amp-sdlc-protocol-controller-67d6755f17221.png.webp"
            "category.id" => array:1 [
              0 => 257
            ]
            "category.name" => array:1 [
              0 => "HDLC IP"
            ]
            "category.slug" => []
            "created_at" => 1399228486
            "id" => "5709"
            "keyfeatures" => """
              <ul>\r\n
              \t<li>Controller for both the SDLC and HDLC (ISO 13239) transmission protocols\r\n
              \t<ul>\r\n
              \t\t<li>Based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC), operating in SDLC Mode</li>\r\n
              \t\t<li>Additional features support HDLC and proprietary serial protocols.</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Safety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t<ul>\r\n
              \t\t<li>Implements TMR for all internal registers &nbsp;</li>\r\n
              \t\t<li>Delivered with a complete DO-254 Certification Data Package</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Frame Formatting\r\n
              \t<ul>\r\n
              \t\t<li>Programmable preamble pattern and preamble length</li>\r\n
              \t\t<li>Programmable inter-frame space</li>\r\n
              \t\t<li>Single- or double-byte address field</li>\r\n
              \t\t<li>Address filtering allowing multicast and broadcast</li>\r\n
              \t\t<li>Raw transmit and receive testing modes</li>\r\n
              \t\t<li>Back-to-back transmit &amp; back-to-back receive</li>\r\n
              \t\t<li>NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding &amp; Decoding</li>\r\n
              \t\t<li>Bit Stuffing and Bit Stripping</li>\r\n
              \t\t<li>16-bit (CRC-16, CCITT or IBM) and 32-bit (CRC-32) frame check sequence</li>\r\n
              \t\t<li>CRC, Bit-stuffing/stripping, and abort and idle sequences detection can be independently enabled/disabled</li>\r\n
              \t\t<li>Receiver FIFO Packet counter</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Serial Link Interface\r\n
              \t<ul>\r\n
              \t\t<li>Full or Half Duplex</li>\r\n
              \t\t<li>Programmable Baud Rate</li>\r\n
              \t\t<li>Modem Controls (RTSn/CTSn)</li>\r\n
              \t\t<li>Collision detection</li>\r\n
              \t\t<li>Internal baud generator, or external transmit clock with strobe</li>\r\n
              \t\t<li>Automatic receive clock recovery, or external receive clock with strobe</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Easy to Integrate\r\n
              \t<ul>\r\n
              \t\t<li>Suitable for interrupt-based or polling-based operation</li>\r\n
              \t\t<li>Configurable size, transmit &amp; receive FIFOs</li>\r\n
              \t\t<li>80XC152-like control&nbsp;status registers</li>\r\n
              \t\t<li>APB or AXI4-Lite</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              </ul>
              """
            "keyfeatures_cn" => ""
            "keywords" => ""
            "logo" => "cast-66bb475b9ffc0.webp"
            "logo2" => "cast-66bb475b9ffc0.webp"
            "name" => "asic.node"
            "overview" => """
              <p>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</p>\r\n
              \r\n
              <p>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;</p>\r\n
              \r\n
              <p>The controller&rsquo;s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud&nbsp;rate is programmable and limited only by the link drivers and the core&rsquo;s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. &nbsp;</p>\r\n
              \r\n
              <p>The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.</p>\r\n
              \r\n
              <p>The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.&nbsp;</p>
              """
            "overview_cn" => ""
            "partnumber" => "HSDLC"
            "priority" => 1
            "priority_taxo" => 1
            "productTypes" => array:1 [
              0 => "sip"
            ]
            "provider.id" => 3
            "provider.name" => "CAST"
            "provider.object" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            "provider.priority" => 751
            "provider.slug" => "cast"
            "published_as_new_at" => 0
            "seofeatures" => """
              <ul>\r\n
              \t<li>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols.</li>\r\n
              \t<li>It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</li>\r\n
              \t<li>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors.</li>\r\n
              </ul>
              """
            "seofeatures_cn" => ""
            "shortdescription" => "HDLC & SDLC Protocol Controller"
            "shortdescription_cn" => ""
            "slug" => "hdlc-amp-sdlc-protocol-controller-ip"
            "sortable_id" => 5709
            "taxo0" => array:1 [
              0 => 1
            ]
            "taxo1" => array:1 [
              0 => 6
            ]
            "taxo2" => array:1 [
              0 => 257
            ]
            "taxo3" => []
            "taxo4" => []
            "taxo5" => []
            "taxo6" => []
            "taxo7" => []
            "taxo8" => []
            "text_high_priority" => "HSDLC HDLC & SDLC Protocol Controller CAST"
            "text_low_priority" => """
              The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and Synchronous (SDLC) protocols. It is based on Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode  adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;\r\n
              \r\n
              The operates as peripheral easy integrate with both modern legacy processors. status registers are accessible via an APB generic 80C51-like bus interface comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;\r\n
              \r\n
              The controller&rsquo;s great flexibility enables variety serial link setups. provides two independent interfaces one transmitting receiving data. Both provide control drivers full- half-duplex can be programmed use hardware flow (RTS/CTS) it also detect collisions. baud&nbsp;rate programmable limited only by core&rsquo;s clock frequency. derives receive from received data uses externally provided clock. &nbsp;\r\n
              \r\n
              The available versions: Normal Safety-Enhanced. Safety-Enhanced version triple-modular redundancy (TMR) full immunity single-bit upsets errors complies Design Assurance Level A (DAL-A) DO-254 standard.\r\n
              \r\n
              The designed reuse rigorously verified scan-ready. Although manage links contains no latches tri-states fully synchronous single domain. Verilog RTL targeted FPGA netlist. Deliverables everything required successful implementation including sample scripts extensive testbench documentation.&nbsp; \r\n
              \tController (ISO 13239) protocols\r\n
              \t\r\n
              \t\tBased operating Mode\r\n
              \t\tAdditional protocols.\r\n
              \t\r\n
              \t\r\n
              \tSafety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t\r\n
              \t\tImplements TMR all internal &nbsp;\r\n
              \t\tDelivered complete Certification Package\r\n
              \t\r\n
              \t\r\n
              \tFlexible Frame Formatting\r\n
              \t\r\n
              \t\tProgrammable preamble pattern length\r\n
              \t\tProgrammable inter-frame space\r\n
              \t\tSingle- double-byte address field\r\n
              \t\tAddress filtering allowing multicast broadcast\r\n
              \t\tRaw transmit testing modes\r\n
              \t\tBack-to-back &amp; back-to-back receive\r\n
              \t\tNRZ NRZI Bi-Phase-S Manchester Encoding Decoding\r\n
              \t\tBit Stuffing Bit Stripping\r\n
              \t\t16-bit (CRC-16 CCITT IBM) 32-bit (CRC-32) check sequence\r\n
              \t\tCRC Bit-stuffing/stripping abort idle sequences detection independently enabled/disabled\r\n
              \t\tReceiver FIFO Packet counter\r\n
              \t\r\n
              \t\r\n
              \tFlexible Interface\r\n
              \t\r\n
              \t\tFull Half Duplex\r\n
              \t\tProgrammable Baud Rate\r\n
              \t\tModem Controls (RTSn/CTSn)\r\n
              \t\tCollision detection\r\n
              \t\tInternal baud generator external strobe\r\n
              \t\tAutomatic recovery strobe\r\n
              \t\r\n
              \t\r\n
              \tEasy Integrate\r\n
              \t\r\n
              \t\tSuitable polling-based operation\r\n
              \t\tConfigurable size FIFOs\r\n
              \t\t80XC152-like control&nbsp;status registers\r\n
              \t\tAPB AXI4-Lite\r\n
              \t\r\n
              \t\r\n
              """
            "text_medium_priority" => ""
            "updated_at" => 1742398313
          ]
          "highlight" => array:2 [
            "text_high_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
            "text_low_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
          ]
          "highlights" => array:2 [
            0 => array:3 [
              "field" => "text_low_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
            1 => array:3 [
              "field" => "text_high_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
          ]
          "text_match" => 1763176949298495490
          "text_match_info" => array:7 [
            "best_field_score" => "2211897868288"
            "best_field_weight" => 15
            "fields_matched" => 2
            "num_tokens_dropped" => 0
            "score" => "1763176949298495490"
            "tokens_matched" => 3
            "typo_prefix_score" => 0
          ]
        ]
      ]
      "out_of" => 18250
      "page" => 1
      "request_params" => array:4 [
        "collection_name" => "product_semiiphub"
        "first_q" => "DO-254 HDLC & SDLC"
        "per_page" => 10
        "q" => "DO-254 HDLC & SDLC"
      ]
      "search_cutoff" => false
      "search_time_ms" => 0
    ]
    2 => array:8 [
      "facet_counts" => array:6 [
        0 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "{"id":3,"name":"CAST","providerslug":"cast"}"
              "value" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            ]
          ]
          "field_name" => "provider.object"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
        1 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        2 => array:4 [
          "counts" => []
          "field_name" => "asic.foundry_node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        3 => array:4 [
          "counts" => []
          "field_name" => "asic.node_foundry"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        4 => array:4 [
          "counts" => []
          "field_name" => "asic.node"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 0
          ]
        ]
        5 => array:4 [
          "counts" => array:1 [
            0 => array:3 [
              "count" => 1
              "highlighted" => "sip"
              "value" => "sip"
            ]
          ]
          "field_name" => "productTypes"
          "sampled" => false
          "stats" => array:1 [
            "total_values" => 1
          ]
        ]
      ]
      "found" => 1
      "hits" => array:1 [
        0 => array:5 [
          "document" => array:48 [
            "asic.foundry" => []
            "asic.foundry_node" => []
            "asic.foundry_node_process" => []
            "asic.node" => []
            "asic.node_foundry" => []
            "blockdiagram" => "/upload/catalog/product/blockdiagram/5709/icon_hdlc-amp-sdlc-protocol-controller-67d6755f17221.png.webp"
            "category.id" => array:1 [
              0 => 257
            ]
            "category.name" => array:1 [
              0 => "HDLC IP"
            ]
            "category.slug" => []
            "created_at" => 1399228486
            "id" => "5709"
            "keyfeatures" => """
              <ul>\r\n
              \t<li>Controller for both the SDLC and HDLC (ISO 13239) transmission protocols\r\n
              \t<ul>\r\n
              \t\t<li>Based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC), operating in SDLC Mode</li>\r\n
              \t\t<li>Additional features support HDLC and proprietary serial protocols.</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Safety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t<ul>\r\n
              \t\t<li>Implements TMR for all internal registers &nbsp;</li>\r\n
              \t\t<li>Delivered with a complete DO-254 Certification Data Package</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Frame Formatting\r\n
              \t<ul>\r\n
              \t\t<li>Programmable preamble pattern and preamble length</li>\r\n
              \t\t<li>Programmable inter-frame space</li>\r\n
              \t\t<li>Single- or double-byte address field</li>\r\n
              \t\t<li>Address filtering allowing multicast and broadcast</li>\r\n
              \t\t<li>Raw transmit and receive testing modes</li>\r\n
              \t\t<li>Back-to-back transmit &amp; back-to-back receive</li>\r\n
              \t\t<li>NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding &amp; Decoding</li>\r\n
              \t\t<li>Bit Stuffing and Bit Stripping</li>\r\n
              \t\t<li>16-bit (CRC-16, CCITT or IBM) and 32-bit (CRC-32) frame check sequence</li>\r\n
              \t\t<li>CRC, Bit-stuffing/stripping, and abort and idle sequences detection can be independently enabled/disabled</li>\r\n
              \t\t<li>Receiver FIFO Packet counter</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Flexible Serial Link Interface\r\n
              \t<ul>\r\n
              \t\t<li>Full or Half Duplex</li>\r\n
              \t\t<li>Programmable Baud Rate</li>\r\n
              \t\t<li>Modem Controls (RTSn/CTSn)</li>\r\n
              \t\t<li>Collision detection</li>\r\n
              \t\t<li>Internal baud generator, or external transmit clock with strobe</li>\r\n
              \t\t<li>Automatic receive clock recovery, or external receive clock with strobe</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              \t<li>Easy to Integrate\r\n
              \t<ul>\r\n
              \t\t<li>Suitable for interrupt-based or polling-based operation</li>\r\n
              \t\t<li>Configurable size, transmit &amp; receive FIFOs</li>\r\n
              \t\t<li>80XC152-like control&nbsp;status registers</li>\r\n
              \t\t<li>APB or AXI4-Lite</li>\r\n
              \t</ul>\r\n
              \t</li>\r\n
              </ul>
              """
            "keyfeatures_cn" => ""
            "keywords" => ""
            "logo" => "cast-66bb475b9ffc0.webp"
            "logo2" => "cast-66bb475b9ffc0.webp"
            "name" => "asic.node"
            "overview" => """
              <p>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</p>\r\n
              \r\n
              <p>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;</p>\r\n
              \r\n
              <p>The controller&rsquo;s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud&nbsp;rate is programmable and limited only by the link drivers and the core&rsquo;s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock. &nbsp;</p>\r\n
              \r\n
              <p>The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.</p>\r\n
              \r\n
              <p>The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.&nbsp;</p>
              """
            "overview_cn" => ""
            "partnumber" => "HSDLC"
            "priority" => 1
            "priority_taxo" => 1
            "productTypes" => array:1 [
              0 => "sip"
            ]
            "provider.id" => 3
            "provider.name" => "CAST"
            "provider.object" => "{"id":3,"name":"CAST","providerslug":"cast"}"
            "provider.priority" => 751
            "provider.slug" => "cast"
            "published_as_new_at" => 0
            "seofeatures" => """
              <ul>\r\n
              \t<li>The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols.</li>\r\n
              \t<li>It is based on the Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;</li>\r\n
              \t<li>The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors.</li>\r\n
              </ul>
              """
            "seofeatures_cn" => ""
            "shortdescription" => "HDLC & SDLC Protocol Controller"
            "shortdescription_cn" => ""
            "slug" => "hdlc-amp-sdlc-protocol-controller-ip"
            "sortable_id" => 5709
            "taxo0" => array:1 [
              0 => 1
            ]
            "taxo1" => array:1 [
              0 => 6
            ]
            "taxo2" => array:1 [
              0 => 257
            ]
            "taxo3" => []
            "taxo4" => []
            "taxo5" => []
            "taxo6" => []
            "taxo7" => []
            "taxo8" => []
            "text_high_priority" => "HSDLC HDLC & SDLC Protocol Controller CAST"
            "text_low_priority" => """
              The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and Synchronous (SDLC) protocols. It is based on Intel&reg;&nbsp;8XC152 Global Serial Channel (GSC) working in SDLC mode  adds features to support HDLC or proprietary frame transmission under host processor control.&nbsp;\r\n
              \r\n
              The operates as peripheral easy integrate with both modern legacy processors. status registers are accessible via an APB generic 80C51-like bus interface comprehensive set of interrupt signals facilitates interrupt-based operation. &nbsp;&nbsp;\r\n
              \r\n
              The controller&rsquo;s great flexibility enables variety serial link setups. provides two independent interfaces one transmitting receiving data. Both provide control drivers full- half-duplex can be programmed use hardware flow (RTS/CTS) it also detect collisions. baud&nbsp;rate programmable limited only by core&rsquo;s clock frequency. derives receive from received data uses externally provided clock. &nbsp;\r\n
              \r\n
              The available versions: Normal Safety-Enhanced. Safety-Enhanced version triple-modular redundancy (TMR) full immunity single-bit upsets errors complies Design Assurance Level A (DAL-A) DO-254 standard.\r\n
              \r\n
              The designed reuse rigorously verified scan-ready. Although manage links contains no latches tri-states fully synchronous single domain. Verilog RTL targeted FPGA netlist. Deliverables everything required successful implementation including sample scripts extensive testbench documentation.&nbsp; \r\n
              \tController (ISO 13239) protocols\r\n
              \t\r\n
              \t\tBased operating Mode\r\n
              \t\tAdditional protocols.\r\n
              \t\r\n
              \t\r\n
              \tSafety Enhanced DO-254/DAL-A Version (Optional)\r\n
              \t\r\n
              \t\tImplements TMR all internal &nbsp;\r\n
              \t\tDelivered complete Certification Package\r\n
              \t\r\n
              \t\r\n
              \tFlexible Frame Formatting\r\n
              \t\r\n
              \t\tProgrammable preamble pattern length\r\n
              \t\tProgrammable inter-frame space\r\n
              \t\tSingle- double-byte address field\r\n
              \t\tAddress filtering allowing multicast broadcast\r\n
              \t\tRaw transmit testing modes\r\n
              \t\tBack-to-back &amp; back-to-back receive\r\n
              \t\tNRZ NRZI Bi-Phase-S Manchester Encoding Decoding\r\n
              \t\tBit Stuffing Bit Stripping\r\n
              \t\t16-bit (CRC-16 CCITT IBM) 32-bit (CRC-32) check sequence\r\n
              \t\tCRC Bit-stuffing/stripping abort idle sequences detection independently enabled/disabled\r\n
              \t\tReceiver FIFO Packet counter\r\n
              \t\r\n
              \t\r\n
              \tFlexible Interface\r\n
              \t\r\n
              \t\tFull Half Duplex\r\n
              \t\tProgrammable Baud Rate\r\n
              \t\tModem Controls (RTSn/CTSn)\r\n
              \t\tCollision detection\r\n
              \t\tInternal baud generator external strobe\r\n
              \t\tAutomatic recovery strobe\r\n
              \t\r\n
              \t\r\n
              \tEasy Integrate\r\n
              \t\r\n
              \t\tSuitable polling-based operation\r\n
              \t\tConfigurable size FIFOs\r\n
              \t\t80XC152-like control&nbsp;status registers\r\n
              \t\tAPB AXI4-Lite\r\n
              \t\r\n
              \t\r\n
              """
            "text_medium_priority" => ""
            "updated_at" => 1742398313
          ]
          "highlight" => array:2 [
            "text_high_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
            "text_low_priority" => array:2 [
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
          ]
          "highlights" => array:2 [
            0 => array:3 [
              "field" => "text_low_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "High-Level Data Link Control (<mark>HDLC</mark>) and Synchronous (<mark>SDLC</mark>) protocols. It is based"
            ]
            1 => array:3 [
              "field" => "text_high_priority"
              "matched_tokens" => array:2 [
                0 => "HDLC"
                1 => "SDLC"
              ]
              "snippet" => "HSDLC <mark>HDLC</mark> & <mark>SDLC</mark> Protocol Controller CAST"
            ]
          ]
          "text_match" => 1763176949298495490
          "text_match_info" => array:7 [
            "best_field_score" => "2211897868288"
            "best_field_weight" => 15
            "fields_matched" => 2
            "num_tokens_dropped" => 0
            "score" => "1763176949298495490"
            "tokens_matched" => 3
            "typo_prefix_score" => 0
          ]
        ]
      ]
      "out_of" => 18250
      "page" => 1
      "request_params" => array:4 [
        "collection_name" => "product_semiiphub"
        "first_q" => "DO-254 HDLC & SDLC"
        "per_page" => 10
        "q" => "DO-254 HDLC & SDLC"
      ]
      "search_cutoff" => false
      "search_time_ms" => 0
    ]
  ]
]

Do-254 hdlc & sdlc IP

DO-254 HDLC & SDLC IP

Filter

Compare 1 IP from 1 vendors (1 - 1)

HDLC & SDLC Protocol Controller
- The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols.
- It is based on the Intel® 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.
- The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors.

Semiconductor IP

MAIN MENU