DDR Combo PHY IP
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38
IP
from 6 vendors
(1
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10)
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DDR and LPDDR Combo PHY
- Supports multiple combinations of DDR/LPDDR interfaces
- Compliant with JEDEC DDR and LPDDR standards
- Supports all auto calibrations
- Industry leading area and power
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LPDDR5X/5/4X/4 combo PHY at 12nm
- Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- Multiple frequency states
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Compliant with JEDEC JESD209-5B for LPDDR5X/5/4X/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
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DDR5/DDR4/LPDDR5 Combo PHY IP - 4800Mbps (Silicon Proven in TSMC 12FFC)
- Supported DRAM type: DDR5/DDR4/LPDDR5
- Maximum controller clock frequency of 675MHz resulting in maximum DRAM data rate of 5400MT/s for DDR5
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 3200MT/s for DDR4
- Maximum controller clock frequency of 600MHz resulting in maximum DRAM data rate of 4800MT/s for LPDDR5?
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LPDDR5/4x/4 combo PHY on 14nm, 12nm
- Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports 1,2, or 4 ranks
- Multiple frequency states
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DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
- Supports DDR3/DDR2 SDRAM
- DDR3 JEDEC standard 1.5v I/O (SSTL_15- compatible)
- DDR2 JEDEC standard 1.8v I/O (SSTL_18- compatible)
- 16 bits width, Single Channel DDR3/DDR2 SDRAM Interface.
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DDR4/ DDR3 Combo PHY IP - 2400Mbps (Silicon Proven in UMC 28HPC+)
- Supports DDR4/DDR3 SDRAM
- DDR4 JEDEC standard 1.2v I/O (POD_12 I/O)
- DDR3 JEDEC standard 1.5v I/O (SSTL_15-compatible)
- 16 bits width, Single Channel DDR4/DDR3 SDRAM Interface.
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DDR4/ DDR3/ DDR3L Combo PHY IP - 1600Mpbs (Silicon Proven in TSMC 28HPC+)
- Supported DRAM type: DDR3/DDR3L/DDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
- Interface: SSTL15/SSTL135/POD12
- Data path width scales in 16-bit increment
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DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- Interface: SSTL
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
- Data path width scales in 8-bit increment
- Programmable output impedance
