ConnX D2 IP

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  • Tensilica ConnX 110/120
    • Certified ISO 26262:2018 ASIL-compliant
    • VLIW parallelism issuing multiple concurrent operations per cycle
    • 128-bit or 256-bit SIMD
    Block Diagram -- Tensilica ConnX 110/120
  • Tensilica ConnX B10/B20
    • Single-instruction, multiple-data (SIMD) vector processing
    • Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
    Block Diagram -- Tensilica ConnX B10/B20
  • Tensilica DSP IP supports efficient AI/ML processing
    • Powerful DSP Instruction Set Supporting AI/ML Operations.
    • Mixed Workloads.
    • Industry-Leading Performance and Power Efficiency.
    • End-to-End Software Toolchain for All Markets and a Large Number of Frameworks.
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Semiconductor IP