Simulation VIP for SPI

Overview

This Cadence® Verification IP (VIP) provides support for the SPI protocol. The SPI VIP provides a complete bus functional model (BFM) and integrated automatic protocol checks. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the Cadence SPI VIP helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Cadence VIPs run on all major simulators and supports the SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specifications: Samsung SPI based on the Exynos 5250 spec Revision 1.00, Motorola SPI based on Block Guide V03.06 and SafeSPI SPI for Automotive Safety V0.15.

Key Features

  • Full Duplex
    • Simultaneous transfer from Manager and Subordinate
  • Variable Size Shift Registers
    • 8, 16, and 32-bit shift register for Tx and Rx
  • Variable Bus Sizes
    • 8, 16, and 32-bit bus interface
  • Tx and Rx FIFOs
    • Two independent 32-bit wide transmit and receive FIFOs
  • Manager/Subordinate Modes
    • Manager-mode and Subordinate-mode
  • Rx Only
    • Receive-without-transmit operation
  • Slave Select Output
    • SS output
  • Mode Fault Error
    • Mode fault error flag with CPU interrupt capability
  • Clock Polarity
    • Serial clock with programmable polarity and phase
  • Control on Wait Mode
    • Control of SPI operation during wait mode
  • Bidirectional Mode
    • One serial data pin for the interface with external device
  • Low Power Mode
    • Run mode, wait mode and stop mode
  • Timing Delays
    • Timing parameters for SCK and SS signals

    Block Diagram

    Simulation VIP for SPI Block Diagram

    Technical Specifications

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Semiconductor IP