CCSDS AR4JA LDPC IP

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Compare 7 IP from 6 vendors (1 - 7)

CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
CCSDS AR4JA LDPC Decoder & Encoder
- CCSDS AR4JA LDPC Code family is quasi-cyclic
- Irregular parity check matrix
- Run time configuration for more than one code rate (i.e., 1/2, 2/3, 3/4)
CCSDS AR4JA LDPC Encoder/Decoder
- AR4JA LDPC code family is quasi-cyclic.
- Irregular parity check matrix.
- Run time configuration for more than one code rate (i.e., 1/2, 2/3, and 3/4).
- Configurable codeword size that supports 2K, 3K, and 4k information words.
CCSDS AR4JA LDPC Encoder & Decoder
- Support for code rates 1/2, 2/3, and 4/5
- Uncoded block sizes of 1024, 4096,band 16384 bits
- Compliant with “TM Synchronization and Channel Coding, Recommended Standard, CCSDS 131.0-B-3, Blue Book, September 2017”
CCSDS TM AR4JA LDPC Encoder
- CCSDS TM AR4JA compatible
- Rate 1/2, 2/3 and 4/5
- Data lengths of 1024 or 4096 bits
CCSDS LDPC
- The AR4JA LDPC code family is quasi-cyclic.
- Supports the nine code rate (1/2, 2/3, and 4/5) for info block length (1024, 4096 and 16384) bits.
- Compliant with 'LOW DENSITY PARITY CHECK CODES FOR USE IN NEAR-EARTH AND DEEP SPACE APPLICATIONS, CCSDS C. 131.0-B-4, April 2022' standard.
AR4JA LDPC Decoder
- AR4JA LDPC code family is quasi-cyclic.
- Irregular parity check matrix.