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BCH Codec IP

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Compare 54 IP from 21 vendors (1 - 10)
  • BCH Error Correcting Code ECC
    • Asynchronous operation
    • No clocks required.
    • No storage like memories SRAMS/ROMS/FilipFlops used
    • No iterative Feedback in the pipeline
    Block Diagram -- BCH Error Correcting Code ECC
  • BCH ECC Core IP
    • The patent-pending Dynamically Configurable BCH technology is the base for the BCH ECC engine incorporating BCH coders and decoders configurable for a wide range of code-length for high performance and high data rate error corrections.
    • The BCH ECC engine with configurable code-length BCH coders and decoders performs the Inversion-less Berlekamp-Massey Algorithm (IBMA) to generate or decode the ECC code on each clock.
  • BCH Intel® FPGA IP Core
    • The Bose, Chaudhuri, and Hocquenghem (BCH) error correction intellectual property (IP) core is typically used in NAND flash applications
    • The BCH Intel FPGA IP core is often used as a companion code with other forward error correction (FEC) IP cores, such as the Reed-Solomon and low-density parity-check (LDPC) IP cores.
  • DVB-S2X Wideband LDPC/ BCH Encoder
    • Compliant with ETSI EN 302 307’
    • Compliant with ETSI EN 302 307-2’
    • Supports BCH-LDPC all code rates for digital video broadcasting
  • Block Diagram -- BCH Encoder and Decoder IP Core
  • DVB-S2X Wideband LDPC BCH Decoder
    • Improved performance
    • Improved efficiency w.r.t. Shannon’s limit
    • Finer gradation of code rate and SNR
  • DVB-C2 LDPC/ BCH Decoder
    • Irregular Parity Check Matrix
    • Layered Decoding
    • Minimum Sum Algorithm
  • UltraFast BCH Decoder
    • BCH codes are widely used where bit errors are scattered randomly within the codeword. The Ultrafast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, tt achieves outstanding data rates.
    • The design can be parameterized at design-time to support different codeword sizes and code rates. Latency can be adjusted by insertion or removal of pipeline register stages.
  • DVB-S2 LDPC BCH Decoder and Encoder
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
  • DVB-S2X LDPC BCH Decoder and Encoder
    • Improved performance
    • Improved efficiency w.r.t. Shannon’s limit
    • Finer gradation of code rate and SNR
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Semiconductor IP