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Alphawave IP IP

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Search (10,013)
Compare 10,013 IP from 389 vendors (1 - 10)
  • eDP 2.0 Verification IP
    • The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC.
    • The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA.
    • This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.
    Block Diagram -- eDP 2.0 Verification IP
  • Post-Quantum Digital Signature IP Core
    • The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptographic standard defined by NIST FIPS 204.
    • Designed to withstand both classical and quantum computer attacks, ML-DSA ensures the authenticity and integrity of signed  data far into the future.
  • Inline Decrypter & Authenticator IP Core for Automotive
    • The Inline Decrypter and Authenticator IP core enables on-the-fly execution of encrypted and signed code from Flash.
    • It is used to authenticate and decrypt code located in Flash. In addition it is ISO26262 certified (ASIL-D).
    Block Diagram -- Inline Decrypter & Authenticator IP Core for Automotive
  • PKC Multi Hardware Accelerator IP
    • The PKC Multi hardware accelerator is a secure connection engine that can be used to offload the compute intensive Public Key operations (Diffie-Hellman Key Exchange, Signature Generation and Verification), widely used for High-performance TLS Handshake.
    Block Diagram -- PKC Multi Hardware Accelerator IP
  • XMSS Post-Quantum Cryptography IP
    • XMSS is a Post-Quantum Cryptographic (PQC) algorithm, meaning it is mathematically designed to be robust against a cryptanalytic attack using a quantum computer.
    • XMSS is a stateful Hash-Based Signature Scheme that has been recommended by NIST in 2020.
    Block Diagram -- XMSS Post-Quantum Cryptography IP
  • ISO/IEC 7816 Verification IP
    • The ISO/IEC 7816 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs that incorporate contactless communication.
    • The ISO/IEC 7816 VIP is compliant with ISO/IEC 7816 Specifications. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.
    Block Diagram -- ISO/IEC 7816 Verification IP
  • ISO/IEC 14443 Verification IP
    • This VIP provides a comprehensive environment for verifying devices acting as either a Proximity Coupling Device (PCD) or a Proximity Integrated Circuit Card (PICC).
    • Fully compliant with the complete ISO/IEC 14443 standard (Parts 1-4), our VIP is a lightweight, plug-and-play solution designed to ensure rigorous verification, minimize design cycle time, and accelerate your time-to-market.
    Block Diagram -- ISO/IEC 14443 Verification IP
  • Block Diagram -- PMBus 1.5 Verification IP
  • LPC Verification IP
    • The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
    • The LPC VIP is fully compliant with LPC Specification version 1.1
    • The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
    Block Diagram -- LPC Verification IP
  • Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40ULP
    • Embedded Computation Engine for utility billing applications
    • Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
    • Embedded power management for the best resilience to power supply noise
    Block Diagram -- Complete measurement analog front end (AFE) IP for single phase power metering in TSMC 40ULP
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Semiconductor IP