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Search (10,092)
Compare 10,092 IP from 391 vendors (1 - 10)
  • CXL 4 Verification IP
    • Compliant with the CXL 4, 3.2, 2.0 & 1.1 Specifications.
    • Support for all three protocols CXL.IO, CXL.CACHE & CXL.MEM including all CXL device types
    • Support for PCIE Mode & Alternate Protocol Negotiation for CXL Mode
    • Support for 256B flit in 128GT/s with PCIe Gen 6 as well as 64/32/16/8 GT/s speeds with backward compatibility.
    Block Diagram -- CXL 4 Verification IP
  • JESD204E Controller IP
    • The JESD204E Controller IP from Chip Interfaces is an early adopter’s version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters.
    • The JESD204-E IP core supports the UCIe Optimized Link Layer, a dedicated mode to run JESD over UCIe Modules with Line rates up the 64Gbps per bump, and a JESD204D backwards compatible mode called the Unified Link Layer with line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and full FEC support.
    Block Diagram -- JESD204E Controller IP
  • eUSB2V1.2 Controller + PHY IP
    • eUSB2 can support USB high-speed, full-speed, and low-speed operation, as well as the USB 2.0 L1/L2 link power management requirements. In addition, eUSB2 requires no change to the existing USB 2.0 software programming model.
    • eUSB2 also uses the same two data line configurations, eD+ and eD- as USB2 D+ and D-. Vbus and power delivery are not impacted by eUSB2.
    Block Diagram -- eUSB2V1.2 Controller + PHY IP
  • eUSB2V2.0 Controller + PHY IP
    • While traditional eUSB2 meets basic connectivity needs at 480 Mbps, modern SoCs and peripherals demand significantly higher throughput.
    • eUSB2-V2.0 bridges this gap by delivering up to 10× performance improvement, along with better power efficiency and EMI control — without changing the fundamental USB 2.0 software ecosystem.
    Block Diagram -- eUSB2V2.0 Controller + PHY IP
  • RISC-V Debug & Trace IP
    • 10xEngineers Debug & N-Trace IP delivers a unified Debug + Trace solution that provides full-system visibility with low overhead and multi-hart awareness.
    • Standards-compliant debug, real-time trace, and flexible triggering significantly reduce bring-up time and simplify system integration.
    Block Diagram -- RISC-V Debug & Trace IP
  • OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
    • The CT25210 Topology Discovery (TD) IP coordinates all operations required to perform 10BASE-T1S topology discovery measurements. It integrates several functional blocks, each responsible for a specific phase of configuration, training, measurement, and signal handling within the discovery process.
    • At the top level, the TD Manager supervises the measurement flow and configuration setup. Within this block, the TD Mode Manager manages the receive-only operating mode and distributes the necessary clock signals to other TD modules.
    Block Diagram -- OPEN Alliance TC14 10BASE-T1S Topology Discovery IP
  • eFuse Controller IP
    • AMBA 3.0 APB interface for register access
    • Automated eFuse read, program, and reload operations
    • Protection against repeated programming of the same bits
    • Support for 32-bit aligned read/program operations
  • Secure Storage Solution for OTP IP
    • Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
    • System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
    • Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs
    Block Diagram -- Secure Storage Solution for OTP IP
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
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