All Digital ADC IP

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Compare 65 IP from 17 vendors (1 - 10)
  • 24-bit Cap-less ADC PLL-less 2 channels
    • Patented PLL-less solution: generate all the sampling frequency through a single master clock frequency with no need of audio PLL
    • Embedded low noise voltage regulator for best resilience to power supply noise
    Block Diagram -- 24-bit Cap-less ADC PLL-less 2 channels
  • 16b, 10Hz sensor ADC
    • Programmable input range
    • Enhanced input stage enables ADC to quantize inputs between -0.25 and +0.25V
    • Low 1/f noise enabled by using chopped opamps in key parts of circuit
    • Good linearity as ADC uses a 1-bit quantizer
    Block Diagram -- 16b, 10Hz sensor ADC
  • GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital IP
    • Supports L1/E1 and L5/E5 bands for multiple constellations including GPS, Glonass, Galileo, Beidou
    • Integrated Cortex ARM M4 F MCU
    • Accuracy upto 1.5m CEP
    • Multi-tone interference mitigation and pulsed interference mitigation
    Block Diagram -- GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital IP
  • 24-bit Cap-less ADC PLL-less 2 channels
    • Patented PLL-less solution: generate all the sampling frequency through a single master clock frequency with no need of audio PLL
    • Embedded low noise voltage regulator for best resilience to power supply noise
    • Optimal sound recording performance thanks to high dynamic range and Automatic Gain control feature
    Block Diagram -- 24-bit Cap-less ADC PLL-less 2 channels
  • 8-bit Microcontrollers Family
    • Cycle compatible with original implementation
    • Software compatible with 68HC11 industry standard
    • I/O Wrapper making it pin-compatible core
    • SFR registers remapped to any 4KB memory page
  • 8-bit Microcontroller IP - legacy architecture - raplacement of 68HC11K MCU's
    • Cycle compatible with original implementation
    • Software compatible with 68HC11K industry standard
    • I/O Wrapper, making it pin-compatible core
    • SFR registers remapped to any 4KB memory page
  • 8-bit FAST Microcontroller
    • FAST architecture, 4 times faster than the original implementation
    • Software compatible with industry standard 68HC11
    • 10 times faster multiplication
    • 16 times faster division
  • 8-bit FAST Microcontroller
    • FAST architecture, 4 times faster than the original implementation
    • Software compatible with 68HC11 industry standard
    • 10 times faster multiplication
    • 16 times faster division
  • 8-bit FAST Microcontroller
    • FAST architecture - 4 times faster than the original implementation
    • Software compatible with 68HC11 industry standard
    • 10 times faster multiplication
    • 16 times faster division
  • GSMC0.18um 12-Bit 8-Input 1M/200k SAR ADC
    • Process: GSMC 0.18um flash process 1Poly 5Metal
    • Resolution: 12-bit resolution
    • DNL: +/-1.5 LSB, INL: +/-3 LSB
    • Dual Data Rates: 1MSPS/200KSPS
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Semiconductor IP