IP Catalog > AXI4 To/from Stream Scatter-Gather DMA

AXI4 to/from Stream Scatter-Gather DMA IP

Filter
Filter

Login required.

Sign in

Search (2)
Compare 2 IP from 2 vendors (1 - 2)
  • AXI4 to/from AXI4-Stream Scatter-Gather DMA
    • The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
    • The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
    Block Diagram -- AXI4 to/from AXI4-Stream Scatter-Gather DMA
  • AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
    • The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
    • Descriptor Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interface, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
    Block Diagram -- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
×
Semiconductor IP