Avc/h.264 IP

The H264-LD-BP IP core implements a silicon and energy efficient hardware video decoder able to process H.264 streams produced by the H264-E-BPS, H264-E-BPF and H264-E-BIS video encoder cores available from CAST.
The H264-LD-BP is extremely small, requiring less than 70k gates and about 60k bits of infernal memory. Its small silicon footprint, low bandwidth requirements, and zero software-overhead enable extremely cost-effective and low-power ASIC and FPGA implementations.

The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
It implements a hardware decoder with very low latency and high throughput that is suitable for live streaming and other delay-sensitive applications up to full HD resolution.

The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
It Implements an ultra-high throughput, UHD/4K capable hardware encoder that is optimized for ultra-low-latency video streaming at low bit rates.

The H264-E-BPS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
It Implements an energy-efficient hardware architecture that is optimized for ultra-low-latency video streaming at low bit rates.

The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
The encoder core has a small silicon footprint—approximately 220K gates and 280K to 420K bits of SRAM—and requires no external memory (e.g. off-chip DRAM) allowing for very cost-effective and low-power ASIC or FPGA implementations.

This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complete video streaming products.
Hardware reference designs and customization services complete the solution.

AVC/H.264 IP