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100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um
- Master-Slave structured DLL
- Delivers optimized small jitter frequencies
- 0-80 phase selection
- Ultra small size (<.1mm^2) suitable to multiple-usage integration
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Spread Spectrum PLL on TSMC CLN40LP-ULP
- Electrically Programmable Macro for Spread Spectrum Clock Generation
- Fractional divide control option allows fine spread control +0/-1.5% in steps of -0.5%
- Module integrated in Analog Bits standard PLL/Frequency Synthesizer
- Implemented with Analog Bits’ proprietary architecture using logic devices only