25G Ultra Low Latency MAC PCS IP

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Compare 3 IP from 3 vendors (1 - 3)
  • 100G MAC/PCS Ultra Ethernet
    • The IP integrates MAC Layer, RS Sub-Layer and 100G PCS Base-R cores according to IEEE 802.3 standard to provide seamless connection between an application and serdes interfaces
    • 128-bit interface for TX and RX between MAC and the application Serdes interface – configurable to support PAM2 and PAM 4
    Block Diagram -- 100G MAC/PCS Ultra Ethernet
  • Ethernet TSN MAC 10G/25G
    • The Ethernet TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Pre-emption and 802.3br Interspersing Express Traffic.
    • This enables the use of the MAC in high-speed time-critical applications.
    • The Ethernet TSN MAC-core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum.
    Block Diagram -- Ethernet TSN MAC 10G/25G
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Semiconductor IP