2.5D GPU IP

Filter

Compare 10 IP from 4 vendors (1 - 10)

Vector Graphics IP
- Display Resolution: Up to 4K
- ROPS (Pixels Per Cycle) : 1
- API Support:Vector Graphics VGLite API
- Embedded Linux Support
Vector Graphics IP
- Hardware off-load compatiable with virtually all CPU types
- Ultra-compact driver footprint enables DDR-less operation with onboard SRAM
HBM3 PHY IP at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
TSMC N3P Source Sync 3DIO PHY
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N3P Source Sync 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N3P 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
TSMC N5 Source Sync 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
Synopsys Synthesizable 3DIO IP for Flexible Physical Implementation
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
3DIO PHY IP for TSMC N5
- Optimized for heterogeneous integration in 3D stacking
- TSMC N5
2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller
- Programmable Shader engine with a VLIW instruction set
- Command list based DMAs to minimize CPU overhead
- Primitive Rasterizer