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12-bit Extended JPEG Decoder IP

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  • Ultra-Fast Baseline and Extended JPEG Decoder
    • This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.
    • It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.  
    Block Diagram -- Ultra-Fast Baseline and Extended JPEG Decoder
  • Baseline and Extended JPEG Decoder
    • The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.   
    • It decompresses JPEG images, and also video payload for Motion-JPEG container formats.
    Block Diagram -- Baseline and Extended JPEG Decoder
  • JPEG Decoder 8K(YUV422) 48fps@200MHz, (16Sample/clk)
    • 96fps@100MHz
    • 16Sample/clk
    • ISO/IEC 10918-1, ITU-T T.81
    Block Diagram -- JPEG Decoder 8K(YUV422) 48fps@200MHz, (16Sample/clk)
  • 8/10/12-bit Extended JPEG Decoder
    • Baseline & Extended ISO/IEC 10918-1 JPEG Compliance
    • Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
    • Additional Processing Capabilities
    Block Diagram -- 8/10/12-bit Extended JPEG Decoder
  • Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
    • The UHT-JPEG-D core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed to provide all the power needed in modern image and Ultra HD video compression applications.
    • The scalability of this IP core enables highly cost-effective silicon implementations of applications that need to handle massive pixel rates and resolutions.
    • The UHT-JPEG-D is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
    Block Diagram -- Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
  • Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
    • The UHT-JPEG-E core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG encoder, with optional video rate control functionality, designed to provide all the power needed in modern image and Ultra HD video compression applications.
    • The scalability of this IP core enables highly cost-effective silicon implementations of applications that need to handle massive pixel rates and resolutions.
    • The UHT-JPEG-E is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
    Block Diagram -- Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
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