112Gb/s SerDes IP
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29
IP
from 6 vendors
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10)
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112Gbps Serdes USR & XSR
- BIST generator and checker;
- Support data polarity inversion;
- TX/RX status control;
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800G Ethernet IP for AI Application
- Support 1 channel of 800GE, or a combination of up to 8 channels of 100GE, 4 channels of 200GE, and 2 channels of 400GE Ethernet channels
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10G-1.6T Ethernet/FiberChannel/FlexO Core
- PCS layer formed by bonded 2x 400GE PCS in PCS Layer
- Using 32 virtual logical lanes based on 2 x 400GE PCS to reduce power in 800G operation
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10G-800G Ethernet/FiberChannel/FlexO Core
- Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
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112Gbps XSR SerDes IP on TSMC 5/4nm
- TSMC N5/N4 processes
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
- Multiple lane RX & TX Macro with integrated PLLs
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112Gbps XSR SerDes IP on TSMC 12nm
- TSMC 12nm
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
- Multiple lane RX & TX Macro with integrated PLLs
- On chip eye monitor
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112Gbps XSR SerDes IP on TSMC 7/6nm
- TSMC 7nm and 6nm processes
- Die-to-Die in Multi-chip Modules or Chiplets 128-bits TX/RX digital interface
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112G-ELR PAM4 SerDes PHY
- Interoperability
- Maximize beach front bandwidth
- Layout flexibility
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112G-ELR PAM4 SerDes PHY - TSMC 7nm
- TSMC 7nm/6nm FinFET CMOS Process
- Power-optimized for ELR LR and MR links
- Fully autonomous startup and adaptation without requiring ASIC intervention
- 112/56Gbps PAM4 or 56/28/10Gbps NRZ data rates
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112Gbps VSR to extended LR SerDes IP on TSMC N5/N4
- TSMC N5/N4 process
- Excellent performance for VSR to extended LR channels from 1G NRZ to 100Gbps PAM4 data rates