112G-ELR SerDes IP
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112G-ELR PAM4 SerDes PHY
- Interoperability
- Maximize beach front bandwidth
- Layout flexibility
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112G-ELR PAM4 SerDes PHY - TSMC 7nm
- TSMC 7nm/6nm FinFET CMOS Process
- Power-optimized for ELR LR and MR links
- Fully autonomous startup and adaptation without requiring ASIC intervention
- 112/56Gbps PAM4 or 56/28/10Gbps NRZ data rates
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112G-ELR PAM4 SerDes PHY - TSMC 5nm
- TSMC 5nm FinFET CMOS Process
- Power-optimized for ELR and LR links
- Integrated BIST capable of producing and checking PRBS
- 56-112Gbps PAM4 or 1-56Gbps NRZ data rates