10Gb UDP Hardware stack IP

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Compare 12 IP from 6 vendors (1 - 10)
  • 10G UDP IP Stack
    • 10G Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo Frames
    • Transmit and Receive
    • ARP with Cache
    • ICMP (Ping Reply)
    Block Diagram -- 10G UDP IP Stack
  • 10G UDP/IP Hardware Protocol Stack
    • 10G Ethernet
    • IPv4 support
    • Transmit and Receive
  • 1G/10G TCP/IP Hardware Stack
    • The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack.
    • More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from — or even the presence of — a system processor.
    Block Diagram -- 1G/10G TCP/IP Hardware Stack
  • UDP/IP – 10 GbE Protocol Hardware Stack
    • 10 GbE network links
    • Low latency, high-performance wire-line performance
    • Internet Protocol (IP) Packet Processor:
    • User Datagram Protocol (UDP) Packet Processor:
    Block Diagram -- UDP/IP – 10 GbE Protocol Hardware Stack
  • 10G UDP Offload Engine UOE+MAC+PCIe+Host_IF Ultra-Low Latency (SXUOE+PCIe)
    • Highly customizable hardware IP Core. Easily portable to ASIC flow, Xilinx/Altera
    • FPGAs or Structured/ASIC flow.
    • Provides Ultra-Low latency and highest bandwidth (NETWORK PROVEN)
    Block Diagram -- 10G UDP Offload Engine UOE+MAC+PCIe+Host_IF Ultra-Low Latency (SXUOE+PCIe)
  • 10G UDP Offload Engine UOE+MAC+Host_IF Ultra-Low Latency (SXUOE)
    • INT 15011 is the only SOC IP Core that implements a full 10G bit UDP Stack in Handcrafted, Ultra-High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation.
    • It provides the lowest latency and highest performance in the industry, No exceptions…..

     

    Block Diagram -- 10G UDP Offload Engine UOE+MAC+Host_IF Ultra-Low Latency (SXUOE)
  • 10G/25G UDP/IP Hardware Protocol Stack
    • Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
    • Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps  even in processor-less SoC designs. 
    Block Diagram -- 10G/25G UDP/IP Hardware Protocol Stack
  • 40G/50G UDP/IP Hardware Protocol Stack
    • Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
    • Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 50Gbps even in processor-less SoC designs. 
    Block Diagram -- 40G/50G UDP/IP Hardware Protocol Stack
  • 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
    • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
    • Seventh Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
    • All stages of Full TCP stack implemented in High performance hardware
    Block Diagram -- 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
  • UDP/IP Offload Engine (UOE)
    • Implements RFC 768 for UDP.
    • Implements RFC 791 for IPv4.
    • Implements RFC 2460 for IPv6.
    Block Diagram -- UDP/IP Offload Engine (UOE)
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