10G Ultra-low latency TCP/IP + MAC + PCS IP

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Compare 4 IP from 1 vendors (1 - 4)
  • 10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
    • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
    • Fifth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
    • All stages of Full TCP stack implemented in High performance hardware
    Block Diagram -- 10G TCP Offload Engine+MAC+Host_IF Ultra-Low Latency (SXTOE)
  • 10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
    • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
    • Provides lowest latency and highest bandwidth (NETWORK PROVEN)
    Block Diagram -- 10G TCP Offload Engine+MAC+PCIe+Host_IF Very-Low Latency (XTOE+PCIe)
  • 10 G bit TCP Offload Engine + PCIe/DMA SOC IP
    • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
    • Fourth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and TCP protocol proven.
    Block Diagram -- 10 G bit TCP Offload Engine + PCIe/DMA  SOC IP
  • 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
    • Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
    • Seventh Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
    • All stages of Full TCP stack implemented in High performance hardware
    Block Diagram -- 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
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