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100 Gbps Polar Decoder IP

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Compare 57 IP from 22 vendors (1 - 10)
  • 2.8 Gbps LVDS IO
    • Different bump options for optimum usage of I/O ring
    • Power down feature for saving power
    Block Diagram -- 2.8 Gbps LVDS IO
  • 2 Gbps Rail to Rail LVDS receiver
    • TSMC CMOS 65 nm
    • 1.2 V CMOS input and output logic signals
    • 2 Gbps (DDR MODE) switching rates
    Block Diagram -- 2 Gbps Rail to Rail LVDS receiver
  • 1.2 Gbps LVDS transmitter/receiver
    • TSMC CMOS 180 nm
    • 3.3 V power supply
    • 1.2 Gbps (DDR MODE) switching rates (600 MHz)
    • Half-duplex or full-duplex operation mode
    Block Diagram -- 1.2 Gbps LVDS transmitter/receiver
  • Rail to rail LVDS receiver 1 Gbps
    • iHP SiGe BiCMOS 0.13 um
    • 3.3 V power supply
    • 1 Gbps (DDR MODE) switching rates
    • Conforms to TIA/EIA-644 LVDS standards without hysteresis
    Block Diagram -- Rail to rail LVDS receiver 1 Gbps
  • 1 Gbps DDR rail to rail LVDS receiver
    • TSMC CMOS 0.065 um.
    • 2.5 V analog power supply.
    • 1.2 V digital power supply.
    Block Diagram -- 1 Gbps DDR rail to rail LVDS receiver
  • Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
    • 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
    Block Diagram -- Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
  • SNOW-V Stream Cipher Engine
    • The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems.
    • It conforms to the official SNOW-V mechanism, published in 2019 by the IACR Transactions on Symmetric Cryptology, as an extensive revision of SNOW 3G stream cipher.
    Block Diagram -- SNOW-V Stream Cipher Engine
  • Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
    • The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data.
    • Its flexible data path is suitable to scale from 100 Gbps to 2.4 Tbps to provide a tailored engine with minimal area for your application.
    • The FIFO-like data interface makes it possible to perform frame processing for many different protocols, including MACsec, IPsec, and OTN security. 
    Block Diagram -- Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
  • Pipelined AES-GCM/CTR Core
    • Scalable architecture configurable from 18 to 128 bits/cycle (up to 128Gbps @ 1GHz)
    • Flow-through design
    • Interleaved capabilities on any number of contexts
    • Stall mitigation when context switching
  • Trans Impedance Amplifier
    • Up to 100 Gbps data rate
    • NRZ option available
    • Global Foundries Fotonix™ process (45SPCLO)
    • GDS ready
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