LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pin (OUTp) to receive data and the control pins (EN_RX, EN_RES, EN_CM) to configure the state of the receiver. EN_RES enables the on-chip 100 Ohm resistor. EN_CM enable input common-mode voltage for mode receiving AC coupled. Pins BP_RX and BPC_RX to gets voltage reference from receiver bias. PAD_INp and PAD_INn are complementary input to connect to the bonding pads. This LVDS receiver does not employ hysteresis, and therefore does not comply with the hysteresis requirement of the TIA and IEEE standards for LVDS differential signaling at the specified rates.
The LVDS receiver is designed on iHP SiGe BiCMOS 0.13 um technology.
Rail to rail LVDS receiver 1 Gbps
Overview
Key Features
- iHP SiGe BiCMOS 0.13 um
- 3.3 V power supply
- 1 Gbps (DDR MODE) switching rates
- Conforms to TIA/EIA-644 LVDS standards without hysteresis
- Rail to rail input range
- Temperature range: -40 °C to + 85 °C
- Optimized for pad-limited layout design
- Portable to other technologies (upon request)
Applications
- Point-to-point data receiver
- Multidrop buses
- Clock distribution
- Backplane receiver
- Backplane data receiver
- Cable data receiver
Deliverables
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Technical Specifications
Foundry, Node
iHP SiGe BiCMOS 0.13 um
Maturity
Pre-silicon verification
Availability
Now