100 G Ethernet MAC & PCS IP Core

Overview

Key Features

•  MAC Core Features
  •  Implements a 320-bit CGMII interface operating at 312.5 MHz for 100G EMAC
  •  Implements 802.3bd specification with ability to generate and recognize PFC pause frames
  •  Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on    transmit and receive respectively.
  •  The application interface is designed as a 512-bit non-segmented (start of a new frame on next 512-bit word) interface operating at    312.5MHz.
•  PCS Core Features (Common)
  •  Implements 100GBase-R PCS core compliant with IEEE 802.3ba Specifications.
  •  Implements a 320-bit CGMII interface operating at 312.5MHz for 100G Ethernet.
  •  Implements 64b/66b encoding/decoding for transmit and receive PCS.
  •  Implements 100G scrambling/descrambling using 802.3ba specified polynomial 1 + x39 + x58
  •  Implements Multi-Lane Distribution (MLD) across 20 Virtual Lanes (VLs)
  •  Implements periodic insertion of Alignment Marker (AM) on the transmit path and deletion on the receive path
  •  Implements 66-bit block synchronization and Alignment Marker Lock machines as specified in 802.3ba specifications.

Benefits

•  Ethernet IP solution implements two user (application) side interfaces. The register configuration and control port is a 32-bit AXI4-Lite    interface. A 512-bit non-segmented AXI-4 streaming bus at 312.5MHz is used to interface with the MAC block. Additionally, an interface    wrapper is provided to support segmented interface operation at lower clock speeds.
• 100Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels.

Block Diagram

Technical Specifications