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Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core

Overview

Intel® Stratix® 10 FPGA H-Tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard.

The Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA intellectual property (IP) core provides access to this hard IP at Ethernet data rates of 100 Gbps. The IP core is included in the Intel® FPGA IP library and is available from the Intel® Quartus® Prime Pro Edition software IP catalog. The IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation.

The 100GBASE-R4 Ethernet channel maps to four 25.78125 Gbps links. The FPGA serial transceivers are compliant with the IEEE 802.3-2015 High Speed Ethernet Standard CAUI-4 specification. The IP core configures the transceivers to implement the relevant specification for your IP core variation. You can connect the transceiver interfaces directly to an external physical medium dependent (PMD) optical module or to another device.

The IP core is designed to the IEEE 802.3-2015 High Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets. All Intel® Stratix® 10 FPGA H-Tile hard IP for Ethernet IP core variations are in full-duplex mode.

Key Features

  • PHY:
    • Hard IP logic that interfaces seamlessly to Intel® Stratix® 10 FPGA 25.78125 Gbps serial transceivers.
    • LAUI or CAUI-4 external interface consisting of two or four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
    • Supports LAUI or CAUI-4 links based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
    • Supports auto-negotiation (AN) as defined in IEEE Standard 802.3-2915 Clause 73.
    • Support link training (LT) as defined in IEEE Standard 802.3-2915 Clauses 92 and 93.
    • Receiver (RX) skew variation tolerance that exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 80.5 requirements.
  • Frame structure control:
    • Support for jumbo packets.
    • RX cyclic redundancy check (CRC) pass-through control.
    • 1,000 bits RX PCS lane skew tolerance for 100G links, which exceeds the IEEE 802.3-2015 High Speed Ethernet Standard Clause 82.2.12 requirements.
    • Optional per-packet transceiver (TX) CRC generation and insertion.
    • RX and TX preamble pass-through options for applications that require proprietary user management information transfer.
    • Optional TX MAC source address insertion.
    • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length on the Ethernet link. Optional per-packet disabling of this feature.
    • TX error insertion capability supports client invalidation of in-progress input to TX client interface.
    • Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte inter-packet gap (IPG) minimum average, or allow the user to drive the IPG from the client interface.
  • Frame monitoring and statistics:
    • RX CRC checking and error reporting.
    • Optional RX strict Start Frame Delimiter (SFD) checking per IEEE specification.
    • Optional RX strict preamble checking per IEEE specification.
    • RX malformed packet checking per IEEE specification.
    • Received control frame type indication.
    • Statistics counters.
    • Snapshot feature for precisely timed capture of statistics counter values.
    • Optional fault signaling: detects and reports local fault and generates remote fault, with support for unidirectional link fault as defined in IEEE 802.3-2015 High Speed Ethernet Standard Clause 66.
  • Flex E:
    • Optional 100GE constant bit rate (CBR) with TX and RX PCS66 scrambler/descrambler.
  • Flow control:
    • Optional IEEE 802.3-2015 Ethernet Standard Clause 31 Ethernet flow control operation using the pause registers or pause interface.
    • Optional priority-based flow control that complies with the IEEE Standard 802.1Q-201 - Amendment 17: Priority-based Flow Control.
    • Pause frame filtering control.
    • Software can dynamically toggle local TX MAC data flow to support selective input flow cut-off.
  • Optical Transport Network:
    • Optional 25/50GE constant bit rate (CBR) with TX and RX PCS66 bit encoding and scrambling disabled.
    • Optional 25/50GE CBR with full MAC and PCS 66-bit features.
  • User system interface:
    • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
    • Avalon-ST datapath interface connects the MAC to client logic with the start of frame in the most significant byte (MSB) in MAC+PCS variations. Interface for 100GBASE-R4 variations has 512 bits, to ensure the data rate despite this RX client interface SOP alignment and RX and TX preamble pass-through option.
    • MII datapath interface connects the PCS to client logic in PCS-only variations. Interface for 100GBASE- R4 variations has 256 bits.
    • Hardware and software reset control.
    • Supports Synchronous Ethernet (Sync-E) by providing a clock data recovery (CDR) output signal to the device fabric.
  • Debug and testability:
    • Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
    • Optional parallel loopback (TX to RX) at the MAC or at the PCS for self-diagnostic testing.
    • Bit-interleaved parity error counters to monitor bit errors per PCS lane.
    • RX PCS error block counters to monitor errors during and between frames.
    • Malformed and dropped packet counters.
    • High bit error rate (BER) detection to monitor link bit error rates over all PCS lanes.
    • Optional scrambled idle test pattern generation and checking.
    • Snapshot feature for precisely timed capture of statistics counter values.
    • TX error insertion capability supports test and debug.
    • Optional access to Intel® FPGA Debug Host Endpoint (ADME) for debugging or monitoring PHY signal integrity.

Block Diagram

Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core Block Diagram

Technical Specifications

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