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AMBA AXI IP

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Compare 200 AMBA AXI IP from 30 vendors (1 - 10)
  • Tessent Bus Monitor
    • Full transaction and trace-level visibility of on-chip bus traffic
    • Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
    • Supports AXI, ACE, ACE-lite
    • Run-time configurable
    Block Diagram -- Tessent Bus Monitor
  • PCIe 5.0 Controller with AXI
    • Comprises complete PCIe 5.0 interface subsystem with Rambus PCIe 5.0 PHY
    • Supports the PCI Express 5.0 rev. 1.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8, 16, 32 and 64-bit) specifications
    • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    Block Diagram -- PCIe 5.0 Controller with AXI
  • PCIe 4.0 Controller with AXI
    • Internal data path size automatically scales up or down (64-, 256- bits) based on link max. speed and width for reduced gate count and optimal throughput
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code
    • Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
    • Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
    Block Diagram -- PCIe 4.0 Controller with AXI
  • AHB Octal SPI Controller with Execute in Place
    • Compatible with many industry-standard serial FLASH devices
    • Execute-in-place (XIP)
    • AMBA AXI4 interface
    Block Diagram -- AHB Octal SPI Controller with Execute in Place
  • CodaCache® Last Level Cache IP
    • Standalone IP
    • 1.2 GHz frequency in 16FF+TT process
    • Protocol interoperability: AMBA AXI 4
    Block Diagram -- CodaCache® Last Level Cache IP
  • RapidIO to AXI Bridge (RAB)
    • Compliant with RapidIO specification, Revision 4.0
    • Compliant to AMBA AXI protocol v4
    • Supports 32-bit or 38-bit addressing
    • AXI PIO operation with configurable number of AXI Slaves
    Block Diagram -- RapidIO to AXI Bridge (RAB)
  • SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
    • Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
    • Sub-LVDS differential PHY signaling
    Block Diagram -- SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
  • AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
    • The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
    • Descriptor Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interface, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
    Block Diagram -- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
  • AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
    • The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
    • Control is managed by Descriptors initialized by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
    Block Diagram -- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
  • AXI QSPI with Execute in Place
    • Compatible with many industry-standard serial FLASH devices
    • Execute-in-place (XIP)
    • AMBA AXI4 interface
    Block Diagram -- AXI QSPI with Execute in Place
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