AMBA AXI IP

AXI5 VIP is Compliant with the latest ARM™ AMBA AXI5 & AXI5 lite.
It is also compatible with AXI3, AXI4 Protocol Specification v2.0 referred to as AXI4 and AXI4-Lite.
Supports Unique ID feature for both read and write transactions.
Supports MTE(Memory Tagging Extension) feature to detect memory safety violations.

Compliant to AMBA® AXI4 specifications from ARM and
supports for all variants of AXI4, AXI4-Lite and AXI4 Stream.
Support for all type of AMBA AXI4 devices.
Strong protocol checking Bus Monitor which also provides statistics of the transactions.

The AMBA-AXI VIP provides a complete solution for verification of AMBA-AXI protocol version 2.0
The AXI verification IP is fully compatible with standard AXI 3 protocol
This VIP is supported natively in System Verilog UVM

The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4

The RapidlO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with the native RapidlO Controller (GRIO) to provide RapidlO interface on one side and AXI interface on the system side.
The Bridge has been architectured to interface with a RapidlO controller used as a Host or device.
The RIO-AXI BRIDGE uses high speed multi-channel DMA Messaging and data streaming controllers to match the bandwidth requirements of the RIO solution.

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
It is expected that the AXI clock and the AHB clock are derived from the same clock source, and that the period of the AHB Lite clock is an integer multiple of the AXI clock in the range [1,16].

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.

The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB Lite bus transaction on a second (asynchronous) clock domain. This allows two completely independent AHB-Lite systems to communicate and share data.
The bridge is implemented as two state machines - one on the initial or “A” domain and another on the secondary or “B” domain, and several synchronizers.

Interfaces AXI bus to external SRAM or Parallel Flash devices
AMBA® AXI Compatible
Supports 8-bit, 16-bit, 32-bit and 64-bit external modes
Supports byte (8-bit), halfword (16-bit), word (32-bit) and dword (64-bit) internal accesses