High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard. Results have a latency of only 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
Floating-point Multiplier
Overview
Key Features
- Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
- Supplied as human readable VHDL (or Verilog) source code
- 32-bit floating-point arithmetic
- IEEE 754 compliant1
- High-speed fully pipelined architecture
- Only 4 clock-cycles of latency
Block Diagram
Applications
- Floating-point pipelines and arithmetic units
- Floating-point processors
Technical Specifications
Short description
Floating-point Multiplier
Vendor
Vendor Name
Foundry, Node
All
Availability
Immediate