Binary-PSK Demodulator

Overview

Key Features

• 16-bit signed input data samples
• Automatic carrier acquisition
• Fast carrier acquisition time
• No complex PLL setup or tuning required
• Practical symbol rates of up to 10 Mbps
• Simple connectivity to an external ADC
• Typical FPGA sample rates of 200 MHz+
• Small implementation size

Benefits

• Technology independent soft IP Core
• Suitable for FPGA, SoC and ASIC
• Supplied as human-readable source code
• One-time license fee with unlimited use
• Field tested and market proven
• Any custom modification on request

Block Diagram

Applications

• Software defined radio
• Short to medium-range telemetry
• IF, SRD and ISM band devices
• Low cost / low power RF applications
• Applications where data packets are transmitted in short discrete bursts

Deliverables

• VHDL source-code (or Verilog on request)
• Simulation test bench
• Examples and scripts
• Full pdf datasheet
• One-to-one technical support
• One years warranty and maintenance

Technical Specifications